An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems

Autores
Sanchez, Raúl M.; Reyes, Benjamín T.; Pola, Ariel L.; Hueda, Mario R.
Año de publicación
2016
Idioma
inglés
Tipo de recurso
documento de conferencia
Estado
versión publicada
Descripción
Fil: Sanchez, Raúl M. Fundación Fulgor; Argentina.
Fil: Reyes, Benjamín T. Consejo Nacional de Investigaciones Científicas y Técnicas. Laboratorio de Comunicaciones Digitales; Argentina.
Fil: Pola, Ariel L. Fundación Fulgor; Argentina.
Fil: Hueda, Mario R. Consejo Nacional de Investigaciones Científicas y Técnicas. Laboratorio de Comunicaciones Digitales; Argentina.
This work describes a 1 Gb/s digital communication system implemented on an FPGA-based platform to investigate mixed-signal calibration techniques of time-interleaved analog-to-digital converters (TI-ADCs). Design of multi-gigabit TI-ADCs is of great interest for next generation digital communication systems such as optical coherent networks. In these applications, mismatches of the sampling time, gain, offset, and frequency response among the interleaves of a TI-ADC limit the performance of the converter unless they are compensated. Typically, long computer simulation run time is required to evaluate the performance of mixed-signal calibration algorithms. We show that the FPGA-based system described in this paper drastically reduces the emulation time by more than hundreds of magnitude orders. The proposed FPGA framework includes: (i) a diagnostic and control unit built upon an embedded processor NIOSII, (ii) DSP blocks to implement the transmitter and the receiver, and (iii) a Gaussian number generator to emulate the noise channel component. Experimental results with a 2 GS/s 6-bit CMOS TI-ADC demonstrate the excellent capability of the implemented FPGA-based emulator to evaluate the performance of a mixed-signal calibration algorithm.
http://dx.doi.org/10.1109/LASCAS.2016.7451041
Fil: Sanchez, Raúl M. Fundación Fulgor; Argentina.
Fil: Reyes, Benjamín T. Consejo Nacional de Investigaciones Científicas y Técnicas. Laboratorio de Comunicaciones Digitales; Argentina.
Fil: Pola, Ariel L. Fundación Fulgor; Argentina.
Fil: Hueda, Mario R. Consejo Nacional de Investigaciones Científicas y Técnicas. Laboratorio de Comunicaciones Digitales; Argentina.
Telecomunicaciones
Materia
Digital
Communication
FPGA
Mixed-signal
Nivel de accesibilidad
acceso abierto
Condiciones de uso
Repositorio
Repositorio Digital Universitario (UNC)
Institución
Universidad Nacional de Córdoba
OAI Identificador
oai:rdu.unc.edu.ar:11086/553345

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repository_id_str 2572
network_name_str Repositorio Digital Universitario (UNC)
spelling An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systemsSanchez, Raúl M.Reyes, Benjamín T.Pola, Ariel L.Hueda, Mario R.DigitalCommunicationFPGAMixed-signalFil: Sanchez, Raúl M. Fundación Fulgor; Argentina.Fil: Reyes, Benjamín T. Consejo Nacional de Investigaciones Científicas y Técnicas. Laboratorio de Comunicaciones Digitales; Argentina.Fil: Pola, Ariel L. Fundación Fulgor; Argentina.Fil: Hueda, Mario R. Consejo Nacional de Investigaciones Científicas y Técnicas. Laboratorio de Comunicaciones Digitales; Argentina.This work describes a 1 Gb/s digital communication system implemented on an FPGA-based platform to investigate mixed-signal calibration techniques of time-interleaved analog-to-digital converters (TI-ADCs). Design of multi-gigabit TI-ADCs is of great interest for next generation digital communication systems such as optical coherent networks. In these applications, mismatches of the sampling time, gain, offset, and frequency response among the interleaves of a TI-ADC limit the performance of the converter unless they are compensated. Typically, long computer simulation run time is required to evaluate the performance of mixed-signal calibration algorithms. We show that the FPGA-based system described in this paper drastically reduces the emulation time by more than hundreds of magnitude orders. The proposed FPGA framework includes: (i) a diagnostic and control unit built upon an embedded processor NIOSII, (ii) DSP blocks to implement the transmitter and the receiver, and (iii) a Gaussian number generator to emulate the noise channel component. Experimental results with a 2 GS/s 6-bit CMOS TI-ADC demonstrate the excellent capability of the implemented FPGA-based emulator to evaluate the performance of a mixed-signal calibration algorithm.http://dx.doi.org/10.1109/LASCAS.2016.7451041Fil: Sanchez, Raúl M. Fundación Fulgor; Argentina.Fil: Reyes, Benjamín T. Consejo Nacional de Investigaciones Científicas y Técnicas. Laboratorio de Comunicaciones Digitales; Argentina.Fil: Pola, Ariel L. Fundación Fulgor; Argentina.Fil: Hueda, Mario R. Consejo Nacional de Investigaciones Científicas y Técnicas. Laboratorio de Comunicaciones Digitales; Argentina.Telecomunicaciones2016info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionhttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdfhttp://hdl.handle.net/11086/553345enginfo:eu-repo/semantics/openAccessreponame:Repositorio Digital Universitario (UNC)instname:Universidad Nacional de Córdobainstacron:UNC2025-09-04T12:31:51Zoai:rdu.unc.edu.ar:11086/553345Institucionalhttps://rdu.unc.edu.ar/Universidad públicaNo correspondehttp://rdu.unc.edu.ar/oai/snrdoca.unc@gmail.comArgentinaNo correspondeNo correspondeNo correspondeopendoar:25722025-09-04 12:31:51.931Repositorio Digital Universitario (UNC) - Universidad Nacional de Córdobafalse
dc.title.none.fl_str_mv An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems
title An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems
spellingShingle An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems
Sanchez, Raúl M.
Digital
Communication
FPGA
Mixed-signal
title_short An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems
title_full An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems
title_fullStr An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems
title_full_unstemmed An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems
title_sort An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems
dc.creator.none.fl_str_mv Sanchez, Raúl M.
Reyes, Benjamín T.
Pola, Ariel L.
Hueda, Mario R.
author Sanchez, Raúl M.
author_facet Sanchez, Raúl M.
Reyes, Benjamín T.
Pola, Ariel L.
Hueda, Mario R.
author_role author
author2 Reyes, Benjamín T.
Pola, Ariel L.
Hueda, Mario R.
author2_role author
author
author
dc.subject.none.fl_str_mv Digital
Communication
FPGA
Mixed-signal
topic Digital
Communication
FPGA
Mixed-signal
dc.description.none.fl_txt_mv Fil: Sanchez, Raúl M. Fundación Fulgor; Argentina.
Fil: Reyes, Benjamín T. Consejo Nacional de Investigaciones Científicas y Técnicas. Laboratorio de Comunicaciones Digitales; Argentina.
Fil: Pola, Ariel L. Fundación Fulgor; Argentina.
Fil: Hueda, Mario R. Consejo Nacional de Investigaciones Científicas y Técnicas. Laboratorio de Comunicaciones Digitales; Argentina.
This work describes a 1 Gb/s digital communication system implemented on an FPGA-based platform to investigate mixed-signal calibration techniques of time-interleaved analog-to-digital converters (TI-ADCs). Design of multi-gigabit TI-ADCs is of great interest for next generation digital communication systems such as optical coherent networks. In these applications, mismatches of the sampling time, gain, offset, and frequency response among the interleaves of a TI-ADC limit the performance of the converter unless they are compensated. Typically, long computer simulation run time is required to evaluate the performance of mixed-signal calibration algorithms. We show that the FPGA-based system described in this paper drastically reduces the emulation time by more than hundreds of magnitude orders. The proposed FPGA framework includes: (i) a diagnostic and control unit built upon an embedded processor NIOSII, (ii) DSP blocks to implement the transmitter and the receiver, and (iii) a Gaussian number generator to emulate the noise channel component. Experimental results with a 2 GS/s 6-bit CMOS TI-ADC demonstrate the excellent capability of the implemented FPGA-based emulator to evaluate the performance of a mixed-signal calibration algorithm.
http://dx.doi.org/10.1109/LASCAS.2016.7451041
Fil: Sanchez, Raúl M. Fundación Fulgor; Argentina.
Fil: Reyes, Benjamín T. Consejo Nacional de Investigaciones Científicas y Técnicas. Laboratorio de Comunicaciones Digitales; Argentina.
Fil: Pola, Ariel L. Fundación Fulgor; Argentina.
Fil: Hueda, Mario R. Consejo Nacional de Investigaciones Científicas y Técnicas. Laboratorio de Comunicaciones Digitales; Argentina.
Telecomunicaciones
description Fil: Sanchez, Raúl M. Fundación Fulgor; Argentina.
publishDate 2016
dc.date.none.fl_str_mv 2016
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info:eu-repo/semantics/publishedVersion
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dc.identifier.none.fl_str_mv http://hdl.handle.net/11086/553345
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reponame_str Repositorio Digital Universitario (UNC)
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instname_str Universidad Nacional de Córdoba
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repository.name.fl_str_mv Repositorio Digital Universitario (UNC) - Universidad Nacional de Córdoba
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