Real-time SSVEP measurements through Lock-in detection in FPGA-based platform

Autores
Oliva, Matías Javier; Guerrero, Federico Nicolás; García, Pablo Andrés; Spinelli, Enrique Mario
Año de publicación
2023
Idioma
inglés
Tipo de recurso
documento de conferencia
Estado
versión publicada
Descripción
In this work, a method for measuring steady-state visually evoked potentials using the Lock-In technique is presented. The proposed method in- volves acquiring the electroencephalography signal through channel averaging from an ADS1299 sigma-delta converter, without the need for additional hardware to accommodate the signal and processing in real-time using an Intel MAX10 FPGA, while visual stimuli synchronized with the sampling and pro- cessing are generated. The result is a robust platform that allows determining a user's attention focus on visual stimuli flickering at 14.70, 16.67, and 19.23 Hz. The initial experimental tests of the system with three subjects validated the platform, obtaining an average signal-to-noise ratio of 3.2 in the detection, with a maximum of 6.2 in the case of an experienced SSVEP user.
Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales
Materia
Ingeniería
SSVEP
FPGA
EEG
Lock-in
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by-nc-nd/4.0/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/160849
Acceder
id SEDICI_6c0a2d0ac6a1d607ff3a75a58d10d2b7
oai_identifier_str oai:sedici.unlp.edu.ar:10915/160849
network_acronym_str SEDICI
repository_id_str 1329
network_name_str SEDICI (UNLP)
spelling Real-time SSVEP measurements through Lock-in detection in FPGA-based platformOliva, Matías JavierGuerrero, Federico NicolásGarcía, Pablo AndrésSpinelli, Enrique MarioIngenieríaSSVEPFPGAEEGLock-inIn this work, a method for measuring steady-state visually evoked potentials using the Lock-In technique is presented. The proposed method in- volves acquiring the electroencephalography signal through channel averaging from an ADS1299 sigma-delta converter, without the need for additional hardware to accommodate the signal and processing in real-time using an Intel MAX10 FPGA, while visual stimuli synchronized with the sampling and pro- cessing are generated. The result is a robust platform that allows determining a user's attention focus on visual stimuli flickering at 14.70, 16.67, and 19.23 Hz. The initial experimental tests of the system with three subjects validated the platform, obtaining an average signal-to-noise ratio of 3.2 in the detection, with a maximum of 6.2 in the case of an experienced SSVEP user.Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales2023-10info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdfhttp://sedici.unlp.edu.ar/handle/10915/160849enginfo:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-nd/4.0/Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-03T11:14:06Zoai:sedici.unlp.edu.ar:10915/160849Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-03 11:14:06.189SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv Real-time SSVEP measurements through Lock-in detection in FPGA-based platform
title Real-time SSVEP measurements through Lock-in detection in FPGA-based platform
spellingShingle Real-time SSVEP measurements through Lock-in detection in FPGA-based platform
Oliva, Matías Javier
Ingeniería
SSVEP
FPGA
EEG
Lock-in
title_short Real-time SSVEP measurements through Lock-in detection in FPGA-based platform
title_full Real-time SSVEP measurements through Lock-in detection in FPGA-based platform
title_fullStr Real-time SSVEP measurements through Lock-in detection in FPGA-based platform
title_full_unstemmed Real-time SSVEP measurements through Lock-in detection in FPGA-based platform
title_sort Real-time SSVEP measurements through Lock-in detection in FPGA-based platform
dc.creator.none.fl_str_mv Oliva, Matías Javier
Guerrero, Federico Nicolás
García, Pablo Andrés
Spinelli, Enrique Mario
author Oliva, Matías Javier
author_facet Oliva, Matías Javier
Guerrero, Federico Nicolás
García, Pablo Andrés
Spinelli, Enrique Mario
author_role author
author2 Guerrero, Federico Nicolás
García, Pablo Andrés
Spinelli, Enrique Mario
author2_role author
author
author
dc.subject.none.fl_str_mv Ingeniería
SSVEP
FPGA
EEG
Lock-in
topic Ingeniería
SSVEP
FPGA
EEG
Lock-in
dc.description.none.fl_txt_mv In this work, a method for measuring steady-state visually evoked potentials using the Lock-In technique is presented. The proposed method in- volves acquiring the electroencephalography signal through channel averaging from an ADS1299 sigma-delta converter, without the need for additional hardware to accommodate the signal and processing in real-time using an Intel MAX10 FPGA, while visual stimuli synchronized with the sampling and pro- cessing are generated. The result is a robust platform that allows determining a user's attention focus on visual stimuli flickering at 14.70, 16.67, and 19.23 Hz. The initial experimental tests of the system with three subjects validated the platform, obtaining an average signal-to-noise ratio of 3.2 in the detection, with a maximum of 6.2 in the case of an experienced SSVEP user.
Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales
description In this work, a method for measuring steady-state visually evoked potentials using the Lock-In technique is presented. The proposed method in- volves acquiring the electroencephalography signal through channel averaging from an ADS1299 sigma-delta converter, without the need for additional hardware to accommodate the signal and processing in real-time using an Intel MAX10 FPGA, while visual stimuli synchronized with the sampling and pro- cessing are generated. The result is a robust platform that allows determining a user's attention focus on visual stimuli flickering at 14.70, 16.67, and 19.23 Hz. The initial experimental tests of the system with three subjects validated the platform, obtaining an average signal-to-noise ratio of 3.2 in the detection, with a maximum of 6.2 in the case of an experienced SSVEP user.
publishDate 2023
dc.date.none.fl_str_mv 2023-10
dc.type.none.fl_str_mv info:eu-repo/semantics/conferenceObject
info:eu-repo/semantics/publishedVersion
Objeto de conferencia
http://purl.org/coar/resource_type/c_5794
info:ar-repo/semantics/documentoDeConferencia
format conferenceObject
status_str publishedVersion
dc.identifier.none.fl_str_mv http://sedici.unlp.edu.ar/handle/10915/160849
url http://sedici.unlp.edu.ar/handle/10915/160849
dc.language.none.fl_str_mv eng
language eng
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by-nc-nd/4.0/
Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc-nd/4.0/
Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0)
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:SEDICI (UNLP)
instname:Universidad Nacional de La Plata
instacron:UNLP
reponame_str SEDICI (UNLP)
collection SEDICI (UNLP)
instname_str Universidad Nacional de La Plata
instacron_str UNLP
institution UNLP
repository.name.fl_str_mv SEDICI (UNLP) - Universidad Nacional de La Plata
repository.mail.fl_str_mv alira@sedici.unlp.edu.ar
_version_ 1842260646159187968
score 13.13397

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