Open-source SoC-FPGA Platform for Signal Processing

Autores
Oliva, Matías Javier; García, Pablo Andrés; Spinelli, Enrique Mario; Veiga, Alejandro Luis
Año de publicación
2023
Idioma
inglés
Tipo de recurso
documento de conferencia
Estado
versión publicada
Descripción
Systems known as SoC-FPGAs have experienced a growing popularity in recent years. This devices integrate field programmable gate arrays with elements such as microprocessors, PLLs and embedded memory blocks. The advantages of this type of systems are clear: great reconfigurability, performance, and energy efficiency, but they come with an negative side: programming and optimizing the applications that use them remains a long and complicated process. In particular, realtime signal processing at high frequencies is an application that can clearly benefit from the advantages of SoC-FPGAs, but the complex workflow assosiated with them usually prevents the designers from taking advantage of its capabilities. In this work, an open source SoC-FPGA platform, specifically intended for signal processing is presented, with the aim of alleviating this workflow. The platform structure is described, specifying the places where the designer may implement their algorithms, and then its operation is demonstrated by acquiring a signal at a maximum sampling frequency of 65 MHz and passing it through a 32th order FIR filter, verifying that the it meets it’s expected theoretical response. The whole system can operate at a maximum frequency of 85 Mhz, has a latency of 16 clock cycles, and uses less than half of the resources of a Cyclone V device.
Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales
Materia
Ingeniería
SoC-FPGA
Signal Processing
Open source
Filtering
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by-nc-nd/4.0/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/160854

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spelling Open-source SoC-FPGA Platform for Signal ProcessingOliva, Matías JavierGarcía, Pablo AndrésSpinelli, Enrique MarioVeiga, Alejandro LuisIngenieríaSoC-FPGASignal ProcessingOpen sourceFilteringSystems known as SoC-FPGAs have experienced a growing popularity in recent years. This devices integrate field programmable gate arrays with elements such as microprocessors, PLLs and embedded memory blocks. The advantages of this type of systems are clear: great reconfigurability, performance, and energy efficiency, but they come with an negative side: programming and optimizing the applications that use them remains a long and complicated process. In particular, realtime signal processing at high frequencies is an application that can clearly benefit from the advantages of SoC-FPGAs, but the complex workflow assosiated with them usually prevents the designers from taking advantage of its capabilities. In this work, an open source SoC-FPGA platform, specifically intended for signal processing is presented, with the aim of alleviating this workflow. The platform structure is described, specifying the places where the designer may implement their algorithms, and then its operation is demonstrated by acquiring a signal at a maximum sampling frequency of 65 MHz and passing it through a 32th order FIR filter, verifying that the it meets it’s expected theoretical response. The whole system can operate at a maximum frequency of 85 Mhz, has a latency of 16 clock cycles, and uses less than half of the resources of a Cyclone V device.Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales2023-03info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdfhttp://sedici.unlp.edu.ar/handle/10915/160854enginfo:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-nd/4.0/Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-03T11:14:06Zoai:sedici.unlp.edu.ar:10915/160854Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-03 11:14:06.183SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv Open-source SoC-FPGA Platform for Signal Processing
title Open-source SoC-FPGA Platform for Signal Processing
spellingShingle Open-source SoC-FPGA Platform for Signal Processing
Oliva, Matías Javier
Ingeniería
SoC-FPGA
Signal Processing
Open source
Filtering
title_short Open-source SoC-FPGA Platform for Signal Processing
title_full Open-source SoC-FPGA Platform for Signal Processing
title_fullStr Open-source SoC-FPGA Platform for Signal Processing
title_full_unstemmed Open-source SoC-FPGA Platform for Signal Processing
title_sort Open-source SoC-FPGA Platform for Signal Processing
dc.creator.none.fl_str_mv Oliva, Matías Javier
García, Pablo Andrés
Spinelli, Enrique Mario
Veiga, Alejandro Luis
author Oliva, Matías Javier
author_facet Oliva, Matías Javier
García, Pablo Andrés
Spinelli, Enrique Mario
Veiga, Alejandro Luis
author_role author
author2 García, Pablo Andrés
Spinelli, Enrique Mario
Veiga, Alejandro Luis
author2_role author
author
author
dc.subject.none.fl_str_mv Ingeniería
SoC-FPGA
Signal Processing
Open source
Filtering
topic Ingeniería
SoC-FPGA
Signal Processing
Open source
Filtering
dc.description.none.fl_txt_mv Systems known as SoC-FPGAs have experienced a growing popularity in recent years. This devices integrate field programmable gate arrays with elements such as microprocessors, PLLs and embedded memory blocks. The advantages of this type of systems are clear: great reconfigurability, performance, and energy efficiency, but they come with an negative side: programming and optimizing the applications that use them remains a long and complicated process. In particular, realtime signal processing at high frequencies is an application that can clearly benefit from the advantages of SoC-FPGAs, but the complex workflow assosiated with them usually prevents the designers from taking advantage of its capabilities. In this work, an open source SoC-FPGA platform, specifically intended for signal processing is presented, with the aim of alleviating this workflow. The platform structure is described, specifying the places where the designer may implement their algorithms, and then its operation is demonstrated by acquiring a signal at a maximum sampling frequency of 65 MHz and passing it through a 32th order FIR filter, verifying that the it meets it’s expected theoretical response. The whole system can operate at a maximum frequency of 85 Mhz, has a latency of 16 clock cycles, and uses less than half of the resources of a Cyclone V device.
Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales
description Systems known as SoC-FPGAs have experienced a growing popularity in recent years. This devices integrate field programmable gate arrays with elements such as microprocessors, PLLs and embedded memory blocks. The advantages of this type of systems are clear: great reconfigurability, performance, and energy efficiency, but they come with an negative side: programming and optimizing the applications that use them remains a long and complicated process. In particular, realtime signal processing at high frequencies is an application that can clearly benefit from the advantages of SoC-FPGAs, but the complex workflow assosiated with them usually prevents the designers from taking advantage of its capabilities. In this work, an open source SoC-FPGA platform, specifically intended for signal processing is presented, with the aim of alleviating this workflow. The platform structure is described, specifying the places where the designer may implement their algorithms, and then its operation is demonstrated by acquiring a signal at a maximum sampling frequency of 65 MHz and passing it through a 32th order FIR filter, verifying that the it meets it’s expected theoretical response. The whole system can operate at a maximum frequency of 85 Mhz, has a latency of 16 clock cycles, and uses less than half of the resources of a Cyclone V device.
publishDate 2023
dc.date.none.fl_str_mv 2023-03
dc.type.none.fl_str_mv info:eu-repo/semantics/conferenceObject
info:eu-repo/semantics/publishedVersion
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dc.language.none.fl_str_mv eng
language eng
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
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Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc-nd/4.0/
Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0)
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repository.name.fl_str_mv SEDICI (UNLP) - Universidad Nacional de La Plata
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