A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

Autores
Reyes, Benjamín Tomás; Paulina, Gustavo German; Sanchez, Raul; Mandolesi, Pablo Sergio; Hueda, Mario Rafael
Año de publicación
2015
Idioma
inglés
Tipo de recurso
artículo
Estado
versión publicada
Descripción
A 2-GS/s 6-bit time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is designed and fabricated in a 0.13 lm CMOS process. The architecture uses 8 time-interleaved track-andhold amplifiers (THA) and 16 asynchronous SAR ADCs. The sampling frequency of the TI-ADC can be set from 200 MHz to more than 2 GHz. The chip includes a programmable delay cell array to adjust up to 25 % the sampling clock phase in each THA, and a multi-channel low voltage differential signaling interface capable of transmitting at full sampling rate (>12 Gb/s), without decimation, off-chip. These blocks make the fabricated ADC an excellent platform to test/evaluate mixed-signal calibration algorithms, which are of great interest for application in high-speed optical systems. Measurements of the fabricated ADC show a peak signal-to-noise-and-distortion ratio of 33.9 dB and a power consumption of 192 mW at 1.2 V.
Fil: Reyes, Benjamín Tomás. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Córdoba. Instituto de Estudios Avanzados En Ingeniería y Tecnología. Universidad Nacional de Córdoba. Facultad de Ciencias exactas Físicas y Naturales. Instituto de Estudios Avanzados En Ingeniería y Tecnología; Argentina
Fil: Paulina, Gustavo German. Fundación Fulgor; Argentina
Fil: Sanchez, Raul. Fundación Fulgor; Argentina
Fil: Mandolesi, Pablo Sergio. Universidad Nacional del Sur; Argentina
Fil: Hueda, Mario Rafael. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Córdoba. Instituto de Estudios Avanzados En Ingeniería y Tecnología. Universidad Nacional de Córdoba. Facultad de Ciencias exactas Físicas y Naturales. Instituto de Estudios Avanzados En Ingeniería y Tecnología; Argentina
Materia
Time-Interleaved Adc
Asynchronous Sar
Optical Receivers
Calibration
Fixed Pattern Noise
Sampling Time Error
Nivel de accesibilidad
acceso abierto
Condiciones de uso
https://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Repositorio
CONICET Digital (CONICET)
Institución
Consejo Nacional de Investigaciones Científicas y Técnicas
OAI Identificador
oai:ri.conicet.gov.ar:11336/69511
Acceder
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oai_identifier_str oai:ri.conicet.gov.ar:11336/69511
network_acronym_str CONICETDig
repository_id_str 3498
network_name_str CONICET Digital (CONICET)
spelling A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniquesReyes, Benjamín TomásPaulina, Gustavo GermanSanchez, RaulMandolesi, Pablo SergioHueda, Mario RafaelTime-Interleaved AdcAsynchronous SarOptical ReceiversCalibrationFixed Pattern NoiseSampling Time Errorhttps://purl.org/becyt/ford/2.2https://purl.org/becyt/ford/2A 2-GS/s 6-bit time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is designed and fabricated in a 0.13 lm CMOS process. The architecture uses 8 time-interleaved track-andhold amplifiers (THA) and 16 asynchronous SAR ADCs. The sampling frequency of the TI-ADC can be set from 200 MHz to more than 2 GHz. The chip includes a programmable delay cell array to adjust up to 25 % the sampling clock phase in each THA, and a multi-channel low voltage differential signaling interface capable of transmitting at full sampling rate (>12 Gb/s), without decimation, off-chip. These blocks make the fabricated ADC an excellent platform to test/evaluate mixed-signal calibration algorithms, which are of great interest for application in high-speed optical systems. Measurements of the fabricated ADC show a peak signal-to-noise-and-distortion ratio of 33.9 dB and a power consumption of 192 mW at 1.2 V.Fil: Reyes, Benjamín Tomás. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Córdoba. Instituto de Estudios Avanzados En Ingeniería y Tecnología. Universidad Nacional de Córdoba. Facultad de Ciencias exactas Físicas y Naturales. Instituto de Estudios Avanzados En Ingeniería y Tecnología; ArgentinaFil: Paulina, Gustavo German. Fundación Fulgor; ArgentinaFil: Sanchez, Raul. Fundación Fulgor; ArgentinaFil: Mandolesi, Pablo Sergio. Universidad Nacional del Sur; ArgentinaFil: Hueda, Mario Rafael. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Córdoba. Instituto de Estudios Avanzados En Ingeniería y Tecnología. Universidad Nacional de Córdoba. Facultad de Ciencias exactas Físicas y Naturales. Instituto de Estudios Avanzados En Ingeniería y Tecnología; ArgentinaSpringer2015-07info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionhttp://purl.org/coar/resource_type/c_6501info:ar-repo/semantics/articuloapplication/pdfapplication/pdfhttp://hdl.handle.net/11336/69511Reyes, Benjamín Tomás; Paulina, Gustavo German; Sanchez, Raul; Mandolesi, Pablo Sergio; Hueda, Mario Rafael; A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques; Springer; Analog Integrated Circuits And Signal Processing; 85; 1; 7-2015; 3-160925-10301573-1979CONICET DigitalCONICETenginfo:eu-repo/semantics/altIdentifier/doi/10.1007/s10470-015-0578-zinfo:eu-repo/semantics/altIdentifier/url/https://link.springer.com/article/10.1007%2Fs10470-015-0578-zinfo:eu-repo/semantics/openAccesshttps://creativecommons.org/licenses/by-nc-sa/2.5/ar/reponame:CONICET Digital (CONICET)instname:Consejo Nacional de Investigaciones Científicas y Técnicas2025-09-03T10:01:54Zoai:ri.conicet.gov.ar:11336/69511instacron:CONICETInstitucionalhttp://ri.conicet.gov.ar/Organismo científico-tecnológicoNo correspondehttp://ri.conicet.gov.ar/oai/requestdasensio@conicet.gov.ar; lcarlino@conicet.gov.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:34982025-09-03 10:01:54.384CONICET Digital (CONICET) - Consejo Nacional de Investigaciones Científicas y Técnicasfalse
dc.title.none.fl_str_mv A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques
title A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques
spellingShingle A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques
Reyes, Benjamín Tomás
Time-Interleaved Adc
Asynchronous Sar
Optical Receivers
Calibration
Fixed Pattern Noise
Sampling Time Error
title_short A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques
title_full A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques
title_fullStr A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques
title_full_unstemmed A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques
title_sort A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques
dc.creator.none.fl_str_mv Reyes, Benjamín Tomás
Paulina, Gustavo German
Sanchez, Raul
Mandolesi, Pablo Sergio
Hueda, Mario Rafael
author Reyes, Benjamín Tomás
author_facet Reyes, Benjamín Tomás
Paulina, Gustavo German
Sanchez, Raul
Mandolesi, Pablo Sergio
Hueda, Mario Rafael
author_role author
author2 Paulina, Gustavo German
Sanchez, Raul
Mandolesi, Pablo Sergio
Hueda, Mario Rafael
author2_role author
author
author
author
dc.subject.none.fl_str_mv Time-Interleaved Adc
Asynchronous Sar
Optical Receivers
Calibration
Fixed Pattern Noise
Sampling Time Error
topic Time-Interleaved Adc
Asynchronous Sar
Optical Receivers
Calibration
Fixed Pattern Noise
Sampling Time Error
purl_subject.fl_str_mv https://purl.org/becyt/ford/2.2
https://purl.org/becyt/ford/2
dc.description.none.fl_txt_mv A 2-GS/s 6-bit time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is designed and fabricated in a 0.13 lm CMOS process. The architecture uses 8 time-interleaved track-andhold amplifiers (THA) and 16 asynchronous SAR ADCs. The sampling frequency of the TI-ADC can be set from 200 MHz to more than 2 GHz. The chip includes a programmable delay cell array to adjust up to 25 % the sampling clock phase in each THA, and a multi-channel low voltage differential signaling interface capable of transmitting at full sampling rate (>12 Gb/s), without decimation, off-chip. These blocks make the fabricated ADC an excellent platform to test/evaluate mixed-signal calibration algorithms, which are of great interest for application in high-speed optical systems. Measurements of the fabricated ADC show a peak signal-to-noise-and-distortion ratio of 33.9 dB and a power consumption of 192 mW at 1.2 V.
Fil: Reyes, Benjamín Tomás. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Córdoba. Instituto de Estudios Avanzados En Ingeniería y Tecnología. Universidad Nacional de Córdoba. Facultad de Ciencias exactas Físicas y Naturales. Instituto de Estudios Avanzados En Ingeniería y Tecnología; Argentina
Fil: Paulina, Gustavo German. Fundación Fulgor; Argentina
Fil: Sanchez, Raul. Fundación Fulgor; Argentina
Fil: Mandolesi, Pablo Sergio. Universidad Nacional del Sur; Argentina
Fil: Hueda, Mario Rafael. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Córdoba. Instituto de Estudios Avanzados En Ingeniería y Tecnología. Universidad Nacional de Córdoba. Facultad de Ciencias exactas Físicas y Naturales. Instituto de Estudios Avanzados En Ingeniería y Tecnología; Argentina
description A 2-GS/s 6-bit time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is designed and fabricated in a 0.13 lm CMOS process. The architecture uses 8 time-interleaved track-andhold amplifiers (THA) and 16 asynchronous SAR ADCs. The sampling frequency of the TI-ADC can be set from 200 MHz to more than 2 GHz. The chip includes a programmable delay cell array to adjust up to 25 % the sampling clock phase in each THA, and a multi-channel low voltage differential signaling interface capable of transmitting at full sampling rate (>12 Gb/s), without decimation, off-chip. These blocks make the fabricated ADC an excellent platform to test/evaluate mixed-signal calibration algorithms, which are of great interest for application in high-speed optical systems. Measurements of the fabricated ADC show a peak signal-to-noise-and-distortion ratio of 33.9 dB and a power consumption of 192 mW at 1.2 V.
publishDate 2015
dc.date.none.fl_str_mv 2015-07
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
http://purl.org/coar/resource_type/c_6501
info:ar-repo/semantics/articulo
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv http://hdl.handle.net/11336/69511
Reyes, Benjamín Tomás; Paulina, Gustavo German; Sanchez, Raul; Mandolesi, Pablo Sergio; Hueda, Mario Rafael; A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques; Springer; Analog Integrated Circuits And Signal Processing; 85; 1; 7-2015; 3-16
0925-1030
1573-1979
CONICET Digital
CONICET
url http://hdl.handle.net/11336/69511
identifier_str_mv Reyes, Benjamín Tomás; Paulina, Gustavo German; Sanchez, Raul; Mandolesi, Pablo Sergio; Hueda, Mario Rafael; A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques; Springer; Analog Integrated Circuits And Signal Processing; 85; 1; 7-2015; 3-16
0925-1030
1573-1979
CONICET Digital
CONICET
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv info:eu-repo/semantics/altIdentifier/doi/10.1007/s10470-015-0578-z
info:eu-repo/semantics/altIdentifier/url/https://link.springer.com/article/10.1007%2Fs10470-015-0578-z
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
https://creativecommons.org/licenses/by-nc-sa/2.5/ar/
eu_rights_str_mv openAccess
rights_invalid_str_mv https://creativecommons.org/licenses/by-nc-sa/2.5/ar/
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv Springer
publisher.none.fl_str_mv Springer
dc.source.none.fl_str_mv reponame:CONICET Digital (CONICET)
instname:Consejo Nacional de Investigaciones Científicas y Técnicas
reponame_str CONICET Digital (CONICET)
collection CONICET Digital (CONICET)
instname_str Consejo Nacional de Investigaciones Científicas y Técnicas
repository.name.fl_str_mv CONICET Digital (CONICET) - Consejo Nacional de Investigaciones Científicas y Técnicas
repository.mail.fl_str_mv dasensio@conicet.gov.ar; lcarlino@conicet.gov.ar
_version_ 1842269724353757184
score 13.13397

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