An improved convergence algorithm to compute ln(x) – FPGA implementations

Autores
Bioul, Géry Jean Antoine; Vázquez, Martín Osvaldo; Acosta, Martín Oriol
Año de publicación
2007
Idioma
inglés
Tipo de recurso
documento de conferencia
Estado
versión publicada
Descripción
This paper presents FPGA implementations of classical algorithms for computing ln(x) with some improvement at the level of the multiplication steps, and step skipping techniques. One starts from a practical implementation of ln(x) computation using a convergence method. The function is approximated by a multiplicative normalization technique, however, thanks to the peculiarity of the multiplicative factor, namely (1 + ai .2-i ), with ai ∈ {-1, 0, 1}, the successive multiplications have been replaced by additions. Doing so, one saves the use of LUT’s and eventually reduces processing time, as addition is generally faster than multiplication. Further, the acceleration technique, based on skipping trivial steps, improves performances. Implementations for FPGA are presented with time and slice cost evaluations. The Xilinx Virtex IV has been used for comparative analysis of 8 to 64-bit logarithm computing devices.
II Workshop de Arquitecturas, Redes y Sistemas Operativos
Red de Universidades con Carreras en Informática (RedUNCI)
Materia
Ciencias Informáticas
Informática
convergence method
multiplicative normalization
xilinx virtex IV
Convergence
Algorithms
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/21591

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network_acronym_str SEDICI
repository_id_str 1329
network_name_str SEDICI (UNLP)
spelling An improved convergence algorithm to compute ln(x) – FPGA implementationsBioul, Géry Jean AntoineVázquez, Martín OsvaldoAcosta, Martín OriolCiencias InformáticasInformáticaconvergence methodmultiplicative normalizationxilinx virtex IVConvergenceAlgorithmsThis paper presents FPGA implementations of classical algorithms for computing ln(x) with some improvement at the level of the multiplication steps, and step skipping techniques. One starts from a practical implementation of ln(x) computation using a convergence method. The function is approximated by a multiplicative normalization technique, however, thanks to the peculiarity of the multiplicative factor, namely (1 + ai .2-i ), with ai ∈ {-1, 0, 1}, the successive multiplications have been replaced by additions. Doing so, one saves the use of LUT’s and eventually reduces processing time, as addition is generally faster than multiplication. Further, the acceleration technique, based on skipping trivial steps, improves performances. Implementations for FPGA are presented with time and slice cost evaluations. The Xilinx Virtex IV has been used for comparative analysis of 8 to 64-bit logarithm computing devices.II Workshop de Arquitecturas, Redes y Sistemas OperativosRed de Universidades con Carreras en Informática (RedUNCI)2007info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdf12-22http://sedici.unlp.edu.ar/handle/10915/21591enginfo:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-sa/2.5/ar/Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-29T10:54:42Zoai:sedici.unlp.edu.ar:10915/21591Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-29 10:54:42.539SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv An improved convergence algorithm to compute ln(x) – FPGA implementations
title An improved convergence algorithm to compute ln(x) – FPGA implementations
spellingShingle An improved convergence algorithm to compute ln(x) – FPGA implementations
Bioul, Géry Jean Antoine
Ciencias Informáticas
Informática
convergence method
multiplicative normalization
xilinx virtex IV
Convergence
Algorithms
title_short An improved convergence algorithm to compute ln(x) – FPGA implementations
title_full An improved convergence algorithm to compute ln(x) – FPGA implementations
title_fullStr An improved convergence algorithm to compute ln(x) – FPGA implementations
title_full_unstemmed An improved convergence algorithm to compute ln(x) – FPGA implementations
title_sort An improved convergence algorithm to compute ln(x) – FPGA implementations
dc.creator.none.fl_str_mv Bioul, Géry Jean Antoine
Vázquez, Martín Osvaldo
Acosta, Martín Oriol
author Bioul, Géry Jean Antoine
author_facet Bioul, Géry Jean Antoine
Vázquez, Martín Osvaldo
Acosta, Martín Oriol
author_role author
author2 Vázquez, Martín Osvaldo
Acosta, Martín Oriol
author2_role author
author
dc.subject.none.fl_str_mv Ciencias Informáticas
Informática
convergence method
multiplicative normalization
xilinx virtex IV
Convergence
Algorithms
topic Ciencias Informáticas
Informática
convergence method
multiplicative normalization
xilinx virtex IV
Convergence
Algorithms
dc.description.none.fl_txt_mv This paper presents FPGA implementations of classical algorithms for computing ln(x) with some improvement at the level of the multiplication steps, and step skipping techniques. One starts from a practical implementation of ln(x) computation using a convergence method. The function is approximated by a multiplicative normalization technique, however, thanks to the peculiarity of the multiplicative factor, namely (1 + ai .2-i ), with ai ∈ {-1, 0, 1}, the successive multiplications have been replaced by additions. Doing so, one saves the use of LUT’s and eventually reduces processing time, as addition is generally faster than multiplication. Further, the acceleration technique, based on skipping trivial steps, improves performances. Implementations for FPGA are presented with time and slice cost evaluations. The Xilinx Virtex IV has been used for comparative analysis of 8 to 64-bit logarithm computing devices.
II Workshop de Arquitecturas, Redes y Sistemas Operativos
Red de Universidades con Carreras en Informática (RedUNCI)
description This paper presents FPGA implementations of classical algorithms for computing ln(x) with some improvement at the level of the multiplication steps, and step skipping techniques. One starts from a practical implementation of ln(x) computation using a convergence method. The function is approximated by a multiplicative normalization technique, however, thanks to the peculiarity of the multiplicative factor, namely (1 + ai .2-i ), with ai ∈ {-1, 0, 1}, the successive multiplications have been replaced by additions. Doing so, one saves the use of LUT’s and eventually reduces processing time, as addition is generally faster than multiplication. Further, the acceleration technique, based on skipping trivial steps, improves performances. Implementations for FPGA are presented with time and slice cost evaluations. The Xilinx Virtex IV has been used for comparative analysis of 8 to 64-bit logarithm computing devices.
publishDate 2007
dc.date.none.fl_str_mv 2007
dc.type.none.fl_str_mv info:eu-repo/semantics/conferenceObject
info:eu-repo/semantics/publishedVersion
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http://purl.org/coar/resource_type/c_5794
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status_str publishedVersion
dc.identifier.none.fl_str_mv http://sedici.unlp.edu.ar/handle/10915/21591
url http://sedici.unlp.edu.ar/handle/10915/21591
dc.language.none.fl_str_mv eng
language eng
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
dc.format.none.fl_str_mv application/pdf
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repository.name.fl_str_mv SEDICI (UNLP) - Universidad Nacional de La Plata
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