Step skipping acceleration techniques on recursive logical circuits : Practical implementations on FPGA

Autores
Vázquez, Martín Osvaldo; Bioul, Géry Jean Antoine
Año de publicación
2008
Idioma
inglés
Tipo de recurso
documento de conferencia
Estado
versión publicada
Descripción
This paper presents step skipping acceleration techniques for a class of convergence algorithms computing arithmetic functions. In particular, an extension of the fast adder carry-skip procedure is carried out for special purpose cellular array circuits implementing iterative logical functions for which some propagating information may be fruitfully computed ahead of the current step output computation. This information is thus carried to the next stage, accelerating the overall calculation. An application is given for the 2´s complement sign changing circuit, then for the step-skipping acceleration circuits used in the implementation of the ln(x) convergence algorithm. FPGA implementations on Xilinx Virtex IV have been achieved with comparative analysis of 32- to 512-bit computing algorithms.
Workshop de Arquitecturas, Redes y Sistemas Operativos (WARSO)
Red de Universidades con Carreras en Informática (RedUNCI)
Materia
Ciencias Informáticas
Convergence
Gate arrays
ln(x)
step skipping
carry-skip adder
Xilinx Virtex 4
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/21576
Acceder
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oai_identifier_str oai:sedici.unlp.edu.ar:10915/21576
network_acronym_str SEDICI
repository_id_str 1329
network_name_str SEDICI (UNLP)
spelling Step skipping acceleration techniques on recursive logical circuits : Practical implementations on FPGAVázquez, Martín OsvaldoBioul, Géry Jean AntoineCiencias InformáticasConvergenceGate arraysln(x)step skippingcarry-skip adderXilinx Virtex 4This paper presents step skipping acceleration techniques for a class of convergence algorithms computing arithmetic functions. In particular, an extension of the fast adder carry-skip procedure is carried out for special purpose cellular array circuits implementing iterative logical functions for which some propagating information may be fruitfully computed ahead of the current step output computation. This information is thus carried to the next stage, accelerating the overall calculation. An application is given for the 2´s complement sign changing circuit, then for the step-skipping acceleration circuits used in the implementation of the ln(x) convergence algorithm. FPGA implementations on Xilinx Virtex IV have been achieved with comparative analysis of 32- to 512-bit computing algorithms.Workshop de Arquitecturas, Redes y Sistemas Operativos (WARSO)Red de Universidades con Carreras en Informática (RedUNCI)2008-10info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdfhttp://sedici.unlp.edu.ar/handle/10915/21576enginfo:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-sa/2.5/ar/Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-29T10:54:42Zoai:sedici.unlp.edu.ar:10915/21576Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-29 10:54:42.499SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv Step skipping acceleration techniques on recursive logical circuits : Practical implementations on FPGA
title Step skipping acceleration techniques on recursive logical circuits : Practical implementations on FPGA
spellingShingle Step skipping acceleration techniques on recursive logical circuits : Practical implementations on FPGA
Vázquez, Martín Osvaldo
Ciencias Informáticas
Convergence
Gate arrays
ln(x)
step skipping
carry-skip adder
Xilinx Virtex 4
title_short Step skipping acceleration techniques on recursive logical circuits : Practical implementations on FPGA
title_full Step skipping acceleration techniques on recursive logical circuits : Practical implementations on FPGA
title_fullStr Step skipping acceleration techniques on recursive logical circuits : Practical implementations on FPGA
title_full_unstemmed Step skipping acceleration techniques on recursive logical circuits : Practical implementations on FPGA
title_sort Step skipping acceleration techniques on recursive logical circuits : Practical implementations on FPGA
dc.creator.none.fl_str_mv Vázquez, Martín Osvaldo
Bioul, Géry Jean Antoine
author Vázquez, Martín Osvaldo
author_facet Vázquez, Martín Osvaldo
Bioul, Géry Jean Antoine
author_role author
author2 Bioul, Géry Jean Antoine
author2_role author
dc.subject.none.fl_str_mv Ciencias Informáticas
Convergence
Gate arrays
ln(x)
step skipping
carry-skip adder
Xilinx Virtex 4
topic Ciencias Informáticas
Convergence
Gate arrays
ln(x)
step skipping
carry-skip adder
Xilinx Virtex 4
dc.description.none.fl_txt_mv This paper presents step skipping acceleration techniques for a class of convergence algorithms computing arithmetic functions. In particular, an extension of the fast adder carry-skip procedure is carried out for special purpose cellular array circuits implementing iterative logical functions for which some propagating information may be fruitfully computed ahead of the current step output computation. This information is thus carried to the next stage, accelerating the overall calculation. An application is given for the 2´s complement sign changing circuit, then for the step-skipping acceleration circuits used in the implementation of the ln(x) convergence algorithm. FPGA implementations on Xilinx Virtex IV have been achieved with comparative analysis of 32- to 512-bit computing algorithms.
Workshop de Arquitecturas, Redes y Sistemas Operativos (WARSO)
Red de Universidades con Carreras en Informática (RedUNCI)
description This paper presents step skipping acceleration techniques for a class of convergence algorithms computing arithmetic functions. In particular, an extension of the fast adder carry-skip procedure is carried out for special purpose cellular array circuits implementing iterative logical functions for which some propagating information may be fruitfully computed ahead of the current step output computation. This information is thus carried to the next stage, accelerating the overall calculation. An application is given for the 2´s complement sign changing circuit, then for the step-skipping acceleration circuits used in the implementation of the ln(x) convergence algorithm. FPGA implementations on Xilinx Virtex IV have been achieved with comparative analysis of 32- to 512-bit computing algorithms.
publishDate 2008
dc.date.none.fl_str_mv 2008-10
dc.type.none.fl_str_mv info:eu-repo/semantics/conferenceObject
info:eu-repo/semantics/publishedVersion
Objeto de conferencia
http://purl.org/coar/resource_type/c_5794
info:ar-repo/semantics/documentoDeConferencia
format conferenceObject
status_str publishedVersion
dc.identifier.none.fl_str_mv http://sedici.unlp.edu.ar/handle/10915/21576
url http://sedici.unlp.edu.ar/handle/10915/21576
dc.language.none.fl_str_mv eng
language eng
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:SEDICI (UNLP)
instname:Universidad Nacional de La Plata
instacron:UNLP
reponame_str SEDICI (UNLP)
collection SEDICI (UNLP)
instname_str Universidad Nacional de La Plata
instacron_str UNLP
institution UNLP
repository.name.fl_str_mv SEDICI (UNLP) - Universidad Nacional de La Plata
repository.mail.fl_str_mv alira@sedici.unlp.edu.ar
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