Utilizing block size variability to enhance instruction fetch rate
- Autores
- Beg, Azam; Chu, Yul
- Año de publicación
- 2007
- Idioma
- inglés
- Tipo de recurso
- artículo
- Estado
- versión publicada
- Descripción
- In the past, instruction fetch speeds have been improved by using cache schemes that capture the actual program flow. In this paper, we elaborate on the architecture and operation of an instruction cache named Variable-Sized Block Cache (VSBC) that also makes use of the dynamic behavior of a program. Current trace-based cache schemes usually have some instructions stored repeatedly; this redundancy is eliminated in VSBC. Our cache also allows storage of basic blocks of arbitrary sizes, in multiple-way cache structure. An overall comparison of trace miss rate and average trace length shows VSBC to be a better performing cache scheme than TC, using SPECint2000 integer benchmarks.
Facultad de Informática - Materia
-
Ciencias Informáticas
Cache memories
Variable-Sized Block Cache (VSBC) - Nivel de accesibilidad
- acceso abierto
- Condiciones de uso
- http://creativecommons.org/licenses/by-nc/3.0/
- Repositorio
.jpg)
- Institución
- Universidad Nacional de La Plata
- OAI Identificador
- oai:sedici.unlp.edu.ar:10915/9548
Ver los metadatos del registro completo
| id |
SEDICI_2c2dfea8a116db16379027295411eb16 |
|---|---|
| oai_identifier_str |
oai:sedici.unlp.edu.ar:10915/9548 |
| network_acronym_str |
SEDICI |
| repository_id_str |
1329 |
| network_name_str |
SEDICI (UNLP) |
| spelling |
Utilizing block size variability to enhance instruction fetch rateBeg, AzamChu, YulCiencias InformáticasCache memoriesVariable-Sized Block Cache (VSBC)In the past, instruction fetch speeds have been improved by using cache schemes that capture the actual program flow. In this paper, we elaborate on the architecture and operation of an instruction cache named Variable-Sized Block Cache (VSBC) that also makes use of the dynamic behavior of a program. Current trace-based cache schemes usually have some instructions stored repeatedly; this redundancy is eliminated in VSBC. Our cache also allows storage of basic blocks of arbitrary sizes, in multiple-way cache structure. An overall comparison of trace miss rate and average trace length shows VSBC to be a better performing cache scheme than TC, using SPECint2000 integer benchmarks.Facultad de Informática2007-04info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionArticulohttp://purl.org/coar/resource_type/c_6501info:ar-repo/semantics/articuloapplication/pdf155-161http://sedici.unlp.edu.ar/handle/10915/9548enginfo:eu-repo/semantics/altIdentifier/url/http://journal.info.unlp.edu.ar/wp-content/uploads/JCST-Apr07-5.pdfinfo:eu-repo/semantics/altIdentifier/issn/1666-6038info:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc/3.0/Creative Commons Attribution-NonCommercial 3.0 Unported (CC BY-NC 3.0)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-10-22T16:32:17Zoai:sedici.unlp.edu.ar:10915/9548Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-10-22 16:32:17.905SEDICI (UNLP) - Universidad Nacional de La Platafalse |
| dc.title.none.fl_str_mv |
Utilizing block size variability to enhance instruction fetch rate |
| title |
Utilizing block size variability to enhance instruction fetch rate |
| spellingShingle |
Utilizing block size variability to enhance instruction fetch rate Beg, Azam Ciencias Informáticas Cache memories Variable-Sized Block Cache (VSBC) |
| title_short |
Utilizing block size variability to enhance instruction fetch rate |
| title_full |
Utilizing block size variability to enhance instruction fetch rate |
| title_fullStr |
Utilizing block size variability to enhance instruction fetch rate |
| title_full_unstemmed |
Utilizing block size variability to enhance instruction fetch rate |
| title_sort |
Utilizing block size variability to enhance instruction fetch rate |
| dc.creator.none.fl_str_mv |
Beg, Azam Chu, Yul |
| author |
Beg, Azam |
| author_facet |
Beg, Azam Chu, Yul |
| author_role |
author |
| author2 |
Chu, Yul |
| author2_role |
author |
| dc.subject.none.fl_str_mv |
Ciencias Informáticas Cache memories Variable-Sized Block Cache (VSBC) |
| topic |
Ciencias Informáticas Cache memories Variable-Sized Block Cache (VSBC) |
| dc.description.none.fl_txt_mv |
In the past, instruction fetch speeds have been improved by using cache schemes that capture the actual program flow. In this paper, we elaborate on the architecture and operation of an instruction cache named Variable-Sized Block Cache (VSBC) that also makes use of the dynamic behavior of a program. Current trace-based cache schemes usually have some instructions stored repeatedly; this redundancy is eliminated in VSBC. Our cache also allows storage of basic blocks of arbitrary sizes, in multiple-way cache structure. An overall comparison of trace miss rate and average trace length shows VSBC to be a better performing cache scheme than TC, using SPECint2000 integer benchmarks. Facultad de Informática |
| description |
In the past, instruction fetch speeds have been improved by using cache schemes that capture the actual program flow. In this paper, we elaborate on the architecture and operation of an instruction cache named Variable-Sized Block Cache (VSBC) that also makes use of the dynamic behavior of a program. Current trace-based cache schemes usually have some instructions stored repeatedly; this redundancy is eliminated in VSBC. Our cache also allows storage of basic blocks of arbitrary sizes, in multiple-way cache structure. An overall comparison of trace miss rate and average trace length shows VSBC to be a better performing cache scheme than TC, using SPECint2000 integer benchmarks. |
| publishDate |
2007 |
| dc.date.none.fl_str_mv |
2007-04 |
| dc.type.none.fl_str_mv |
info:eu-repo/semantics/article info:eu-repo/semantics/publishedVersion Articulo http://purl.org/coar/resource_type/c_6501 info:ar-repo/semantics/articulo |
| format |
article |
| status_str |
publishedVersion |
| dc.identifier.none.fl_str_mv |
http://sedici.unlp.edu.ar/handle/10915/9548 |
| url |
http://sedici.unlp.edu.ar/handle/10915/9548 |
| dc.language.none.fl_str_mv |
eng |
| language |
eng |
| dc.relation.none.fl_str_mv |
info:eu-repo/semantics/altIdentifier/url/http://journal.info.unlp.edu.ar/wp-content/uploads/JCST-Apr07-5.pdf info:eu-repo/semantics/altIdentifier/issn/1666-6038 |
| dc.rights.none.fl_str_mv |
info:eu-repo/semantics/openAccess http://creativecommons.org/licenses/by-nc/3.0/ Creative Commons Attribution-NonCommercial 3.0 Unported (CC BY-NC 3.0) |
| eu_rights_str_mv |
openAccess |
| rights_invalid_str_mv |
http://creativecommons.org/licenses/by-nc/3.0/ Creative Commons Attribution-NonCommercial 3.0 Unported (CC BY-NC 3.0) |
| dc.format.none.fl_str_mv |
application/pdf 155-161 |
| dc.source.none.fl_str_mv |
reponame:SEDICI (UNLP) instname:Universidad Nacional de La Plata instacron:UNLP |
| reponame_str |
SEDICI (UNLP) |
| collection |
SEDICI (UNLP) |
| instname_str |
Universidad Nacional de La Plata |
| instacron_str |
UNLP |
| institution |
UNLP |
| repository.name.fl_str_mv |
SEDICI (UNLP) - Universidad Nacional de La Plata |
| repository.mail.fl_str_mv |
alira@sedici.unlp.edu.ar |
| _version_ |
1846782742870622208 |
| score |
12.982451 |