Cache Sharing Administration for Performance Fairness using D3C Miss Classification in Chip Multi-Processors
- Autores
- Carballal, Claudio A.; Hamkalo, José Luis; Cernuschi-Frías, Bruno
- Año de publicación
- 2011
- Idioma
- inglés
- Tipo de recurso
- documento de conferencia
- Estado
- versión publicada
- Descripción
- This work presents a study of fairness in cache sharing between processes in a chip multiprocessor (CMP). We propose a new algorithm that uses a metric based on the D3C miss classification and LRU Stack Distance, to measure the fairness in the administration of the resources to achieve an increase of the global IPC of all executed processes. Shared cache miss rate, IPC and bandwidth metrics were considered to analyze the simulation results obtained using three test sets. The obtained results showed that the proposed dynamic management policy compared to Capitalist management policy, has a lower global miss rate in shared cache and lower bandwidth usage for each test set studied and fulfills its objective of managing the shared cache space for every process while improving the overall IPC.
Sociedad Argentina de Informática e Investigación Operativa - Materia
-
Ciencias Informáticas
Shared Cache
Multi-Process
CMP
Dynamic Cache Administration
Instrumentation
PIN - Nivel de accesibilidad
- acceso abierto
- Condiciones de uso
- http://creativecommons.org/licenses/by-nc-sa/4.0/
- Repositorio
- Institución
- Universidad Nacional de La Plata
- OAI Identificador
- oai:sedici.unlp.edu.ar:10915/126119
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Cache Sharing Administration for Performance Fairness using D3C Miss Classification in Chip Multi-ProcessorsCarballal, Claudio A.Hamkalo, José LuisCernuschi-Frías, BrunoCiencias InformáticasShared CacheMulti-ProcessCMPDynamic Cache AdministrationInstrumentationPINThis work presents a study of fairness in cache sharing between processes in a chip multiprocessor (CMP). We propose a new algorithm that uses a metric based on the D3C miss classification and LRU Stack Distance, to measure the fairness in the administration of the resources to achieve an increase of the global IPC of all executed processes. Shared cache miss rate, IPC and bandwidth metrics were considered to analyze the simulation results obtained using three test sets. The obtained results showed that the proposed dynamic management policy compared to Capitalist management policy, has a lower global miss rate in shared cache and lower bandwidth usage for each test set studied and fulfills its objective of managing the shared cache space for every process while improving the overall IPC.Sociedad Argentina de Informática e Investigación Operativa2011-08info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdf25-40http://sedici.unlp.edu.ar/handle/10915/126119enginfo:eu-repo/semantics/altIdentifier/url/https://40jaiio.sadio.org.ar/sites/default/files/T2011/HPC/842.pdfinfo:eu-repo/semantics/altIdentifier/issn/1851-9326info:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-sa/4.0/Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-29T11:30:27Zoai:sedici.unlp.edu.ar:10915/126119Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-29 11:30:28.115SEDICI (UNLP) - Universidad Nacional de La Platafalse |
dc.title.none.fl_str_mv |
Cache Sharing Administration for Performance Fairness using D3C Miss Classification in Chip Multi-Processors |
title |
Cache Sharing Administration for Performance Fairness using D3C Miss Classification in Chip Multi-Processors |
spellingShingle |
Cache Sharing Administration for Performance Fairness using D3C Miss Classification in Chip Multi-Processors Carballal, Claudio A. Ciencias Informáticas Shared Cache Multi-Process CMP Dynamic Cache Administration Instrumentation PIN |
title_short |
Cache Sharing Administration for Performance Fairness using D3C Miss Classification in Chip Multi-Processors |
title_full |
Cache Sharing Administration for Performance Fairness using D3C Miss Classification in Chip Multi-Processors |
title_fullStr |
Cache Sharing Administration for Performance Fairness using D3C Miss Classification in Chip Multi-Processors |
title_full_unstemmed |
Cache Sharing Administration for Performance Fairness using D3C Miss Classification in Chip Multi-Processors |
title_sort |
Cache Sharing Administration for Performance Fairness using D3C Miss Classification in Chip Multi-Processors |
dc.creator.none.fl_str_mv |
Carballal, Claudio A. Hamkalo, José Luis Cernuschi-Frías, Bruno |
author |
Carballal, Claudio A. |
author_facet |
Carballal, Claudio A. Hamkalo, José Luis Cernuschi-Frías, Bruno |
author_role |
author |
author2 |
Hamkalo, José Luis Cernuschi-Frías, Bruno |
author2_role |
author author |
dc.subject.none.fl_str_mv |
Ciencias Informáticas Shared Cache Multi-Process CMP Dynamic Cache Administration Instrumentation PIN |
topic |
Ciencias Informáticas Shared Cache Multi-Process CMP Dynamic Cache Administration Instrumentation PIN |
dc.description.none.fl_txt_mv |
This work presents a study of fairness in cache sharing between processes in a chip multiprocessor (CMP). We propose a new algorithm that uses a metric based on the D3C miss classification and LRU Stack Distance, to measure the fairness in the administration of the resources to achieve an increase of the global IPC of all executed processes. Shared cache miss rate, IPC and bandwidth metrics were considered to analyze the simulation results obtained using three test sets. The obtained results showed that the proposed dynamic management policy compared to Capitalist management policy, has a lower global miss rate in shared cache and lower bandwidth usage for each test set studied and fulfills its objective of managing the shared cache space for every process while improving the overall IPC. Sociedad Argentina de Informática e Investigación Operativa |
description |
This work presents a study of fairness in cache sharing between processes in a chip multiprocessor (CMP). We propose a new algorithm that uses a metric based on the D3C miss classification and LRU Stack Distance, to measure the fairness in the administration of the resources to achieve an increase of the global IPC of all executed processes. Shared cache miss rate, IPC and bandwidth metrics were considered to analyze the simulation results obtained using three test sets. The obtained results showed that the proposed dynamic management policy compared to Capitalist management policy, has a lower global miss rate in shared cache and lower bandwidth usage for each test set studied and fulfills its objective of managing the shared cache space for every process while improving the overall IPC. |
publishDate |
2011 |
dc.date.none.fl_str_mv |
2011-08 |
dc.type.none.fl_str_mv |
info:eu-repo/semantics/conferenceObject info:eu-repo/semantics/publishedVersion Objeto de conferencia http://purl.org/coar/resource_type/c_5794 info:ar-repo/semantics/documentoDeConferencia |
format |
conferenceObject |
status_str |
publishedVersion |
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http://sedici.unlp.edu.ar/handle/10915/126119 |
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http://sedici.unlp.edu.ar/handle/10915/126119 |
dc.language.none.fl_str_mv |
eng |
language |
eng |
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dc.rights.none.fl_str_mv |
info:eu-repo/semantics/openAccess http://creativecommons.org/licenses/by-nc-sa/4.0/ Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0) |
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openAccess |
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http://creativecommons.org/licenses/by-nc-sa/4.0/ Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0) |
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