SoC-FPGA systems for the acquisition and processing of electroencephalographic signals

Autores
Oliva, Matias Javier; Arias García, Pablo Andrés; Spinelli, Enrique Mario; Veiga, Alejandro Luis
Año de publicación
2021
Idioma
inglés
Tipo de recurso
artículo
Estado
versión publicada
Descripción
Real-time acquisition and processing of electroencephalographic signals have promising applications in the implementation of brain-computer interfaces. These devices allow the user to control a device without performing motor actions, and are usually made up of a biopotential acquisition stage and a personal computer (PC). This structure is very flexible and appropriate for research, but for final users it is necessary to migrate to an embedded system, eliminating the PC from the scheme. The strict real-time processing requirements of such systems justify the choice of a system on a chip field-programmable gate arrays (SoC-FPGA) for its implementation. This article proposes a platform for the acquisition and processing of electroencephalographic signals using this type of device, which combines the parallelism and speed capabilities of an FPGA with the simplicity of a general-purpose processor on a single chip. In this scheme, the FPGA is in charge of the real-time operation, acquiring and processing the signals, while the processor solves the high-level tasks, with the interconnection between processing elements solved by buses integrated into the chip. The proposed scheme was used to implement a brain-computer interface based on steady-state visual evoked potentials, which was used to command a speller. The first tests of the system show that a selection time of 5 seconds per command can be achieved. The time delay between the user’s selection and the system response has been estimated at 343 µs.
Fil: Oliva, Matias Javier. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; Argentina
Fil: Arias García, Pablo Andrés. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; Argentina
Fil: Spinelli, Enrique Mario. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; Argentina
Fil: Veiga, Alejandro Luis. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; Argentina
Materia
BIOPOTENTIALS
BRAIN-COMPUTER INTERFACES
DIGITAL SYSTEMS DESIGN
SOC-FPGA SYSTEMS
STEADY-STATE EVOKED POTENTIALS
Nivel de accesibilidad
acceso abierto
Condiciones de uso
https://creativecommons.org/licenses/by-sa/2.5/ar/
Repositorio
CONICET Digital (CONICET)
Institución
Consejo Nacional de Investigaciones Científicas y Técnicas
OAI Identificador
oai:ri.conicet.gov.ar:11336/172356
Acceder
id CONICETDig_cdb1391b9789638f45feef98a8ee1f8f
oai_identifier_str oai:ri.conicet.gov.ar:11336/172356
network_acronym_str CONICETDig
repository_id_str 3498
network_name_str CONICET Digital (CONICET)
spelling SoC-FPGA systems for the acquisition and processing of electroencephalographic signalsOliva, Matias JavierArias García, Pablo AndrésSpinelli, Enrique MarioVeiga, Alejandro LuisBIOPOTENTIALSBRAIN-COMPUTER INTERFACESDIGITAL SYSTEMS DESIGNSOC-FPGA SYSTEMSSTEADY-STATE EVOKED POTENTIALShttps://purl.org/becyt/ford/2.2https://purl.org/becyt/ford/2Real-time acquisition and processing of electroencephalographic signals have promising applications in the implementation of brain-computer interfaces. These devices allow the user to control a device without performing motor actions, and are usually made up of a biopotential acquisition stage and a personal computer (PC). This structure is very flexible and appropriate for research, but for final users it is necessary to migrate to an embedded system, eliminating the PC from the scheme. The strict real-time processing requirements of such systems justify the choice of a system on a chip field-programmable gate arrays (SoC-FPGA) for its implementation. This article proposes a platform for the acquisition and processing of electroencephalographic signals using this type of device, which combines the parallelism and speed capabilities of an FPGA with the simplicity of a general-purpose processor on a single chip. In this scheme, the FPGA is in charge of the real-time operation, acquiring and processing the signals, while the processor solves the high-level tasks, with the interconnection between processing elements solved by buses integrated into the chip. The proposed scheme was used to implement a brain-computer interface based on steady-state visual evoked potentials, which was used to command a speller. The first tests of the system show that a selection time of 5 seconds per command can be achieved. The time delay between the user’s selection and the system response has been estimated at 343 µs.Fil: Oliva, Matias Javier. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; ArgentinaFil: Arias García, Pablo Andrés. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; ArgentinaFil: Spinelli, Enrique Mario. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; ArgentinaFil: Veiga, Alejandro Luis. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; ArgentinaInstitute of Advanced Engineering and Science2021-11-03info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionhttp://purl.org/coar/resource_type/c_6501info:ar-repo/semantics/articuloapplication/pdfapplication/pdfhttp://hdl.handle.net/11336/172356Oliva, Matias Javier; Arias García, Pablo Andrés; Spinelli, Enrique Mario; Veiga, Alejandro Luis; SoC-FPGA systems for the acquisition and processing of electroencephalographic signals; Institute of Advanced Engineering and Science; International Journal of Reconfigurable and Embedded Systems; 10; 3; 3-11-2021; 237-2482089-4864CONICET DigitalCONICETenginfo:eu-repo/semantics/altIdentifier/doi/10.11591/ijres.v10.i3.pp237-248info:eu-repo/semantics/altIdentifier/url/https://ijres.iaescore.com/index.php/IJRES/article/view/20359info:eu-repo/semantics/openAccesshttps://creativecommons.org/licenses/by-sa/2.5/ar/reponame:CONICET Digital (CONICET)instname:Consejo Nacional de Investigaciones Científicas y Técnicas2025-09-03T10:06:41Zoai:ri.conicet.gov.ar:11336/172356instacron:CONICETInstitucionalhttp://ri.conicet.gov.ar/Organismo científico-tecnológicoNo correspondehttp://ri.conicet.gov.ar/oai/requestdasensio@conicet.gov.ar; lcarlino@conicet.gov.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:34982025-09-03 10:06:41.609CONICET Digital (CONICET) - Consejo Nacional de Investigaciones Científicas y Técnicasfalse
dc.title.none.fl_str_mv SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
title SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
spellingShingle SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
Oliva, Matias Javier
BIOPOTENTIALS
BRAIN-COMPUTER INTERFACES
DIGITAL SYSTEMS DESIGN
SOC-FPGA SYSTEMS
STEADY-STATE EVOKED POTENTIALS
title_short SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
title_full SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
title_fullStr SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
title_full_unstemmed SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
title_sort SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
dc.creator.none.fl_str_mv Oliva, Matias Javier
Arias García, Pablo Andrés
Spinelli, Enrique Mario
Veiga, Alejandro Luis
author Oliva, Matias Javier
author_facet Oliva, Matias Javier
Arias García, Pablo Andrés
Spinelli, Enrique Mario
Veiga, Alejandro Luis
author_role author
author2 Arias García, Pablo Andrés
Spinelli, Enrique Mario
Veiga, Alejandro Luis
author2_role author
author
author
dc.subject.none.fl_str_mv BIOPOTENTIALS
BRAIN-COMPUTER INTERFACES
DIGITAL SYSTEMS DESIGN
SOC-FPGA SYSTEMS
STEADY-STATE EVOKED POTENTIALS
topic BIOPOTENTIALS
BRAIN-COMPUTER INTERFACES
DIGITAL SYSTEMS DESIGN
SOC-FPGA SYSTEMS
STEADY-STATE EVOKED POTENTIALS
purl_subject.fl_str_mv https://purl.org/becyt/ford/2.2
https://purl.org/becyt/ford/2
dc.description.none.fl_txt_mv Real-time acquisition and processing of electroencephalographic signals have promising applications in the implementation of brain-computer interfaces. These devices allow the user to control a device without performing motor actions, and are usually made up of a biopotential acquisition stage and a personal computer (PC). This structure is very flexible and appropriate for research, but for final users it is necessary to migrate to an embedded system, eliminating the PC from the scheme. The strict real-time processing requirements of such systems justify the choice of a system on a chip field-programmable gate arrays (SoC-FPGA) for its implementation. This article proposes a platform for the acquisition and processing of electroencephalographic signals using this type of device, which combines the parallelism and speed capabilities of an FPGA with the simplicity of a general-purpose processor on a single chip. In this scheme, the FPGA is in charge of the real-time operation, acquiring and processing the signals, while the processor solves the high-level tasks, with the interconnection between processing elements solved by buses integrated into the chip. The proposed scheme was used to implement a brain-computer interface based on steady-state visual evoked potentials, which was used to command a speller. The first tests of the system show that a selection time of 5 seconds per command can be achieved. The time delay between the user’s selection and the system response has been estimated at 343 µs.
Fil: Oliva, Matias Javier. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; Argentina
Fil: Arias García, Pablo Andrés. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; Argentina
Fil: Spinelli, Enrique Mario. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; Argentina
Fil: Veiga, Alejandro Luis. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; Argentina
description Real-time acquisition and processing of electroencephalographic signals have promising applications in the implementation of brain-computer interfaces. These devices allow the user to control a device without performing motor actions, and are usually made up of a biopotential acquisition stage and a personal computer (PC). This structure is very flexible and appropriate for research, but for final users it is necessary to migrate to an embedded system, eliminating the PC from the scheme. The strict real-time processing requirements of such systems justify the choice of a system on a chip field-programmable gate arrays (SoC-FPGA) for its implementation. This article proposes a platform for the acquisition and processing of electroencephalographic signals using this type of device, which combines the parallelism and speed capabilities of an FPGA with the simplicity of a general-purpose processor on a single chip. In this scheme, the FPGA is in charge of the real-time operation, acquiring and processing the signals, while the processor solves the high-level tasks, with the interconnection between processing elements solved by buses integrated into the chip. The proposed scheme was used to implement a brain-computer interface based on steady-state visual evoked potentials, which was used to command a speller. The first tests of the system show that a selection time of 5 seconds per command can be achieved. The time delay between the user’s selection and the system response has been estimated at 343 µs.
publishDate 2021
dc.date.none.fl_str_mv 2021-11-03
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
http://purl.org/coar/resource_type/c_6501
info:ar-repo/semantics/articulo
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv http://hdl.handle.net/11336/172356
Oliva, Matias Javier; Arias García, Pablo Andrés; Spinelli, Enrique Mario; Veiga, Alejandro Luis; SoC-FPGA systems for the acquisition and processing of electroencephalographic signals; Institute of Advanced Engineering and Science; International Journal of Reconfigurable and Embedded Systems; 10; 3; 3-11-2021; 237-248
2089-4864
CONICET Digital
CONICET
url http://hdl.handle.net/11336/172356
identifier_str_mv Oliva, Matias Javier; Arias García, Pablo Andrés; Spinelli, Enrique Mario; Veiga, Alejandro Luis; SoC-FPGA systems for the acquisition and processing of electroencephalographic signals; Institute of Advanced Engineering and Science; International Journal of Reconfigurable and Embedded Systems; 10; 3; 3-11-2021; 237-248
2089-4864
CONICET Digital
CONICET
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv info:eu-repo/semantics/altIdentifier/doi/10.11591/ijres.v10.i3.pp237-248
info:eu-repo/semantics/altIdentifier/url/https://ijres.iaescore.com/index.php/IJRES/article/view/20359
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
https://creativecommons.org/licenses/by-sa/2.5/ar/
eu_rights_str_mv openAccess
rights_invalid_str_mv https://creativecommons.org/licenses/by-sa/2.5/ar/
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv Institute of Advanced Engineering and Science
publisher.none.fl_str_mv Institute of Advanced Engineering and Science
dc.source.none.fl_str_mv reponame:CONICET Digital (CONICET)
instname:Consejo Nacional de Investigaciones Científicas y Técnicas
reponame_str CONICET Digital (CONICET)
collection CONICET Digital (CONICET)
instname_str Consejo Nacional de Investigaciones Científicas y Técnicas
repository.name.fl_str_mv CONICET Digital (CONICET) - Consejo Nacional de Investigaciones Científicas y Técnicas
repository.mail.fl_str_mv dasensio@conicet.gov.ar; lcarlino@conicet.gov.ar
_version_ 1842269969703763968
score 13.13397

Publicaciones similares