SoC-FPGA systems for the acquisition and processing of electroencephalographic signals

Autores
Oliva, Matías Javier; García, Pablo Andrés; Spinelli, Enrique Mario; Veiga, Alejandro Luis
Año de publicación
2021
Idioma
inglés
Tipo de recurso
artículo
Estado
versión publicada
Descripción
Real-time acquisition and processing of electroencephalographic signals have promising applications in the implementation of brain-computer interfaces. These devices allow the user to control a device without performing motor actions, and are usually made up of a biopotential acquisition stage and a personal computer (PC). This structure is very flexible and appropriate for research, but for final users it is necessary to migrate to an embedded system, eliminating the PC from the scheme. The strict real-time processing requirements of such systems justify the choice of a system on a chip fieldprogrammable gate arrays (SoC-FPGA) for its implementation. This article proposes a platform for the acquisition and processing of electroencephalographic signals using this type of device, which combines the parallelism and speed capabilities of an FPGA with the simplicity of a general-purpose processor on a single chip. In this scheme, the FPGA is in charge of the real-time operation, acquiring and processing the signals, while the processor solves the high-level tasks, with the interconnection between processing elements solved by buses integrated into the chip. The proposed scheme was used to implement a brain-computer interface based on steadystate visual evoked potentials, which was used to command a speller. The first tests of the system show that a selection time of 5 seconds per command can be achieved. The time delay between the user’s selection and the system response has been estimated at 343 µs.
Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales
Materia
Ingeniería Electrónica
Biopotentials
Brain-computer interfaces
Digital systems design
SoC-FPGA systems
Steady-state evoked potentials
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by-sa/4.0/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/160818

id SEDICI_c705fddcafb27631674cdef1e272d564
oai_identifier_str oai:sedici.unlp.edu.ar:10915/160818
network_acronym_str SEDICI
repository_id_str 1329
network_name_str SEDICI (UNLP)
spelling SoC-FPGA systems for the acquisition and processing of electroencephalographic signalsOliva, Matías JavierGarcía, Pablo AndrésSpinelli, Enrique MarioVeiga, Alejandro LuisIngeniería ElectrónicaBiopotentialsBrain-computer interfacesDigital systems designSoC-FPGA systemsSteady-state evoked potentialsReal-time acquisition and processing of electroencephalographic signals have promising applications in the implementation of brain-computer interfaces. These devices allow the user to control a device without performing motor actions, and are usually made up of a biopotential acquisition stage and a personal computer (PC). This structure is very flexible and appropriate for research, but for final users it is necessary to migrate to an embedded system, eliminating the PC from the scheme. The strict real-time processing requirements of such systems justify the choice of a system on a chip fieldprogrammable gate arrays (SoC-FPGA) for its implementation. This article proposes a platform for the acquisition and processing of electroencephalographic signals using this type of device, which combines the parallelism and speed capabilities of an FPGA with the simplicity of a general-purpose processor on a single chip. In this scheme, the FPGA is in charge of the real-time operation, acquiring and processing the signals, while the processor solves the high-level tasks, with the interconnection between processing elements solved by buses integrated into the chip. The proposed scheme was used to implement a brain-computer interface based on steadystate visual evoked potentials, which was used to command a speller. The first tests of the system show that a selection time of 5 seconds per command can be achieved. The time delay between the user’s selection and the system response has been estimated at 343 µs.Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales2021-11-01info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionArticulohttp://purl.org/coar/resource_type/c_6501info:ar-repo/semantics/articuloapplication/pdf237-248http://sedici.unlp.edu.ar/handle/10915/160818enginfo:eu-repo/semantics/altIdentifier/url/https://ijres.iaescore.com/index.php/IJRES/article/view/20359info:eu-repo/semantics/altIdentifier/issn/2089-4864info:eu-repo/semantics/altIdentifier/doi/10.11591/ijres.v10.i3.pp237-248info:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-sa/4.0/Creative Commons Attribution-ShareAlike 4.0 International (CC BY-SA 4.0)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-03T11:14:05Zoai:sedici.unlp.edu.ar:10915/160818Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-03 11:14:05.54SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
title SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
spellingShingle SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
Oliva, Matías Javier
Ingeniería Electrónica
Biopotentials
Brain-computer interfaces
Digital systems design
SoC-FPGA systems
Steady-state evoked potentials
title_short SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
title_full SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
title_fullStr SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
title_full_unstemmed SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
title_sort SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
dc.creator.none.fl_str_mv Oliva, Matías Javier
García, Pablo Andrés
Spinelli, Enrique Mario
Veiga, Alejandro Luis
author Oliva, Matías Javier
author_facet Oliva, Matías Javier
García, Pablo Andrés
Spinelli, Enrique Mario
Veiga, Alejandro Luis
author_role author
author2 García, Pablo Andrés
Spinelli, Enrique Mario
Veiga, Alejandro Luis
author2_role author
author
author
dc.subject.none.fl_str_mv Ingeniería Electrónica
Biopotentials
Brain-computer interfaces
Digital systems design
SoC-FPGA systems
Steady-state evoked potentials
topic Ingeniería Electrónica
Biopotentials
Brain-computer interfaces
Digital systems design
SoC-FPGA systems
Steady-state evoked potentials
dc.description.none.fl_txt_mv Real-time acquisition and processing of electroencephalographic signals have promising applications in the implementation of brain-computer interfaces. These devices allow the user to control a device without performing motor actions, and are usually made up of a biopotential acquisition stage and a personal computer (PC). This structure is very flexible and appropriate for research, but for final users it is necessary to migrate to an embedded system, eliminating the PC from the scheme. The strict real-time processing requirements of such systems justify the choice of a system on a chip fieldprogrammable gate arrays (SoC-FPGA) for its implementation. This article proposes a platform for the acquisition and processing of electroencephalographic signals using this type of device, which combines the parallelism and speed capabilities of an FPGA with the simplicity of a general-purpose processor on a single chip. In this scheme, the FPGA is in charge of the real-time operation, acquiring and processing the signals, while the processor solves the high-level tasks, with the interconnection between processing elements solved by buses integrated into the chip. The proposed scheme was used to implement a brain-computer interface based on steadystate visual evoked potentials, which was used to command a speller. The first tests of the system show that a selection time of 5 seconds per command can be achieved. The time delay between the user’s selection and the system response has been estimated at 343 µs.
Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales
description Real-time acquisition and processing of electroencephalographic signals have promising applications in the implementation of brain-computer interfaces. These devices allow the user to control a device without performing motor actions, and are usually made up of a biopotential acquisition stage and a personal computer (PC). This structure is very flexible and appropriate for research, but for final users it is necessary to migrate to an embedded system, eliminating the PC from the scheme. The strict real-time processing requirements of such systems justify the choice of a system on a chip fieldprogrammable gate arrays (SoC-FPGA) for its implementation. This article proposes a platform for the acquisition and processing of electroencephalographic signals using this type of device, which combines the parallelism and speed capabilities of an FPGA with the simplicity of a general-purpose processor on a single chip. In this scheme, the FPGA is in charge of the real-time operation, acquiring and processing the signals, while the processor solves the high-level tasks, with the interconnection between processing elements solved by buses integrated into the chip. The proposed scheme was used to implement a brain-computer interface based on steadystate visual evoked potentials, which was used to command a speller. The first tests of the system show that a selection time of 5 seconds per command can be achieved. The time delay between the user’s selection and the system response has been estimated at 343 µs.
publishDate 2021
dc.date.none.fl_str_mv 2021-11-01
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
Articulo
http://purl.org/coar/resource_type/c_6501
info:ar-repo/semantics/articulo
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv http://sedici.unlp.edu.ar/handle/10915/160818
url http://sedici.unlp.edu.ar/handle/10915/160818
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv info:eu-repo/semantics/altIdentifier/url/https://ijres.iaescore.com/index.php/IJRES/article/view/20359
info:eu-repo/semantics/altIdentifier/issn/2089-4864
info:eu-repo/semantics/altIdentifier/doi/10.11591/ijres.v10.i3.pp237-248
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by-sa/4.0/
Creative Commons Attribution-ShareAlike 4.0 International (CC BY-SA 4.0)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-sa/4.0/
Creative Commons Attribution-ShareAlike 4.0 International (CC BY-SA 4.0)
dc.format.none.fl_str_mv application/pdf
237-248
dc.source.none.fl_str_mv reponame:SEDICI (UNLP)
instname:Universidad Nacional de La Plata
instacron:UNLP
reponame_str SEDICI (UNLP)
collection SEDICI (UNLP)
instname_str Universidad Nacional de La Plata
instacron_str UNLP
institution UNLP
repository.name.fl_str_mv SEDICI (UNLP) - Universidad Nacional de La Plata
repository.mail.fl_str_mv alira@sedici.unlp.edu.ar
_version_ 1842260646149750784
score 13.13397