Design and implementation of a genetic algorithm with integer number coding for the evolution of FPGAs in space applications

Autores
Quiroga, Juan; Paz, Francisco; Capossio, Juan Pablo
Año de publicación
2012
Idioma
inglés
Tipo de recurso
documento de conferencia
Estado
versión publicada
Descripción
In [1] a form of representation of logic circuits by chains of integer numbers is presented. That type of representation is easy to simulate and to export to FPGA hardware in such a way that, by adding a genetic algorithm (GA), it can be used in an evolutionary process. Because regular GAs utilize binary number coding, one was designed, with all its operators and processes, that uses integer number coding. This evolvable hardware (EH) process was tested with more than 200 hours of runs to determine the effectiveness of the integer coded GA. Results show that, given the proper conditions, the GA is effective in finding solutions that fulfill the required needs of the target system and that this particular EH platform is suitable for applications where fault tolerance capability is required, such as space systems.
Eje: Workshop Arquitectura, redes y sistemas operativos (WARSO)
Red de Universidades con Carreras en Informática (RedUNCI)
Materia
Ciencias Informáticas
Genetic Algorithms
Evolvable Hardware
FPGA
Fault Tolerance
sistema operativo
Algorithms
Architectures
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/23760
Acceder
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oai_identifier_str oai:sedici.unlp.edu.ar:10915/23760
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repository_id_str 1329
network_name_str SEDICI (UNLP)
spelling Design and implementation of a genetic algorithm with integer number coding for the evolution of FPGAs in space applicationsQuiroga, JuanPaz, FranciscoCapossio, Juan PabloCiencias InformáticasGenetic AlgorithmsEvolvable HardwareFPGAFault Tolerancesistema operativoAlgorithmsArchitecturesIn [1] a form of representation of logic circuits by chains of integer numbers is presented. That type of representation is easy to simulate and to export to FPGA hardware in such a way that, by adding a genetic algorithm (GA), it can be used in an evolutionary process. Because regular GAs utilize binary number coding, one was designed, with all its operators and processes, that uses integer number coding. This evolvable hardware (EH) process was tested with more than 200 hours of runs to determine the effectiveness of the integer coded GA. Results show that, given the proper conditions, the GA is effective in finding solutions that fulfill the required needs of the target system and that this particular EH platform is suitable for applications where fault tolerance capability is required, such as space systems.Eje: Workshop Arquitectura, redes y sistemas operativos (WARSO)Red de Universidades con Carreras en Informática (RedUNCI)2012-10info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdfhttp://sedici.unlp.edu.ar/handle/10915/23760enginfo:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-sa/2.5/ar/Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-10-15T10:48:14Zoai:sedici.unlp.edu.ar:10915/23760Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-10-15 10:48:14.222SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv Design and implementation of a genetic algorithm with integer number coding for the evolution of FPGAs in space applications
title Design and implementation of a genetic algorithm with integer number coding for the evolution of FPGAs in space applications
spellingShingle Design and implementation of a genetic algorithm with integer number coding for the evolution of FPGAs in space applications
Quiroga, Juan
Ciencias Informáticas
Genetic Algorithms
Evolvable Hardware
FPGA
Fault Tolerance
sistema operativo
Algorithms
Architectures
title_short Design and implementation of a genetic algorithm with integer number coding for the evolution of FPGAs in space applications
title_full Design and implementation of a genetic algorithm with integer number coding for the evolution of FPGAs in space applications
title_fullStr Design and implementation of a genetic algorithm with integer number coding for the evolution of FPGAs in space applications
title_full_unstemmed Design and implementation of a genetic algorithm with integer number coding for the evolution of FPGAs in space applications
title_sort Design and implementation of a genetic algorithm with integer number coding for the evolution of FPGAs in space applications
dc.creator.none.fl_str_mv Quiroga, Juan
Paz, Francisco
Capossio, Juan Pablo
author Quiroga, Juan
author_facet Quiroga, Juan
Paz, Francisco
Capossio, Juan Pablo
author_role author
author2 Paz, Francisco
Capossio, Juan Pablo
author2_role author
author
dc.subject.none.fl_str_mv Ciencias Informáticas
Genetic Algorithms
Evolvable Hardware
FPGA
Fault Tolerance
sistema operativo
Algorithms
Architectures
topic Ciencias Informáticas
Genetic Algorithms
Evolvable Hardware
FPGA
Fault Tolerance
sistema operativo
Algorithms
Architectures
dc.description.none.fl_txt_mv In [1] a form of representation of logic circuits by chains of integer numbers is presented. That type of representation is easy to simulate and to export to FPGA hardware in such a way that, by adding a genetic algorithm (GA), it can be used in an evolutionary process. Because regular GAs utilize binary number coding, one was designed, with all its operators and processes, that uses integer number coding. This evolvable hardware (EH) process was tested with more than 200 hours of runs to determine the effectiveness of the integer coded GA. Results show that, given the proper conditions, the GA is effective in finding solutions that fulfill the required needs of the target system and that this particular EH platform is suitable for applications where fault tolerance capability is required, such as space systems.
Eje: Workshop Arquitectura, redes y sistemas operativos (WARSO)
Red de Universidades con Carreras en Informática (RedUNCI)
description In [1] a form of representation of logic circuits by chains of integer numbers is presented. That type of representation is easy to simulate and to export to FPGA hardware in such a way that, by adding a genetic algorithm (GA), it can be used in an evolutionary process. Because regular GAs utilize binary number coding, one was designed, with all its operators and processes, that uses integer number coding. This evolvable hardware (EH) process was tested with more than 200 hours of runs to determine the effectiveness of the integer coded GA. Results show that, given the proper conditions, the GA is effective in finding solutions that fulfill the required needs of the target system and that this particular EH platform is suitable for applications where fault tolerance capability is required, such as space systems.
publishDate 2012
dc.date.none.fl_str_mv 2012-10
dc.type.none.fl_str_mv info:eu-repo/semantics/conferenceObject
info:eu-repo/semantics/publishedVersion
Objeto de conferencia
http://purl.org/coar/resource_type/c_5794
info:ar-repo/semantics/documentoDeConferencia
format conferenceObject
status_str publishedVersion
dc.identifier.none.fl_str_mv http://sedici.unlp.edu.ar/handle/10915/23760
url http://sedici.unlp.edu.ar/handle/10915/23760
dc.language.none.fl_str_mv eng
language eng
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:SEDICI (UNLP)
instname:Universidad Nacional de La Plata
instacron:UNLP
reponame_str SEDICI (UNLP)
collection SEDICI (UNLP)
instname_str Universidad Nacional de La Plata
instacron_str UNLP
institution UNLP
repository.name.fl_str_mv SEDICI (UNLP) - Universidad Nacional de La Plata
repository.mail.fl_str_mv alira@sedici.unlp.edu.ar
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