Application of a Genetic Algorithm in a Fault-tolerant Filter

Autores
Lovay, Mónica; Peretti, Gabriela; Romero, Eduardo; Marqués, Carlos
Año de publicación
2013
Idioma
inglés
Tipo de recurso
documento de conferencia
Estado
versión publicada
Descripción
This paper presents an eighth order low-pass filter which has characteristics of fault tolerance through the use of evolvable hardware (EHW). A field programmable analog array (FPAA) is used to implement the filter under study. The reconfiguration process of the filter involves the execution of a genetic algorithm (GA) in an external computer, after a fault is detected. To perform the test of the filter, we assume that a frequency response characterization test is used. A parametric fault model that considers deviations in the values of one of the capacitors or one of the input amplifiers (IA) is used to evaluate the performance of developed GA. The results show that GA finds filter configurations that meet the restrictions set for all the simulated faults. Additionally, this work shows better results compared to those previously obtained using another EHW scheme for the same low-pass filter.
Sociedad Argentina de Informática e Investigación Operativa
Materia
Ciencias Informáticas
evolvable hardware
field programmable analog array
faulttolerant filter
genetic algorithm
multi-objective optimization
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by-nc-sa/4.0/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/76858

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network_name_str SEDICI (UNLP)
spelling Application of a Genetic Algorithm in a Fault-tolerant FilterLovay, MónicaPeretti, GabrielaRomero, EduardoMarqués, CarlosCiencias Informáticasevolvable hardwarefield programmable analog arrayfaulttolerant filtergenetic algorithmmulti-objective optimizationThis paper presents an eighth order low-pass filter which has characteristics of fault tolerance through the use of evolvable hardware (EHW). A field programmable analog array (FPAA) is used to implement the filter under study. The reconfiguration process of the filter involves the execution of a genetic algorithm (GA) in an external computer, after a fault is detected. To perform the test of the filter, we assume that a frequency response characterization test is used. A parametric fault model that considers deviations in the values of one of the capacitors or one of the input amplifiers (IA) is used to evaluate the performance of developed GA. The results show that GA finds filter configurations that meet the restrictions set for all the simulated faults. Additionally, this work shows better results compared to those previously obtained using another EHW scheme for the same low-pass filter.Sociedad Argentina de Informática e Investigación Operativa2013-09info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdf140-151http://sedici.unlp.edu.ar/handle/10915/76858enginfo:eu-repo/semantics/altIdentifier/url/http://42jaiio.sadio.org.ar/proceedings/simposios/Trabajos/AST/13.pdfinfo:eu-repo/semantics/altIdentifier/issn/1850-2806info:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-sa/4.0/Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-03T10:45:40Zoai:sedici.unlp.edu.ar:10915/76858Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-03 10:45:40.739SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv Application of a Genetic Algorithm in a Fault-tolerant Filter
title Application of a Genetic Algorithm in a Fault-tolerant Filter
spellingShingle Application of a Genetic Algorithm in a Fault-tolerant Filter
Lovay, Mónica
Ciencias Informáticas
evolvable hardware
field programmable analog array
faulttolerant filter
genetic algorithm
multi-objective optimization
title_short Application of a Genetic Algorithm in a Fault-tolerant Filter
title_full Application of a Genetic Algorithm in a Fault-tolerant Filter
title_fullStr Application of a Genetic Algorithm in a Fault-tolerant Filter
title_full_unstemmed Application of a Genetic Algorithm in a Fault-tolerant Filter
title_sort Application of a Genetic Algorithm in a Fault-tolerant Filter
dc.creator.none.fl_str_mv Lovay, Mónica
Peretti, Gabriela
Romero, Eduardo
Marqués, Carlos
author Lovay, Mónica
author_facet Lovay, Mónica
Peretti, Gabriela
Romero, Eduardo
Marqués, Carlos
author_role author
author2 Peretti, Gabriela
Romero, Eduardo
Marqués, Carlos
author2_role author
author
author
dc.subject.none.fl_str_mv Ciencias Informáticas
evolvable hardware
field programmable analog array
faulttolerant filter
genetic algorithm
multi-objective optimization
topic Ciencias Informáticas
evolvable hardware
field programmable analog array
faulttolerant filter
genetic algorithm
multi-objective optimization
dc.description.none.fl_txt_mv This paper presents an eighth order low-pass filter which has characteristics of fault tolerance through the use of evolvable hardware (EHW). A field programmable analog array (FPAA) is used to implement the filter under study. The reconfiguration process of the filter involves the execution of a genetic algorithm (GA) in an external computer, after a fault is detected. To perform the test of the filter, we assume that a frequency response characterization test is used. A parametric fault model that considers deviations in the values of one of the capacitors or one of the input amplifiers (IA) is used to evaluate the performance of developed GA. The results show that GA finds filter configurations that meet the restrictions set for all the simulated faults. Additionally, this work shows better results compared to those previously obtained using another EHW scheme for the same low-pass filter.
Sociedad Argentina de Informática e Investigación Operativa
description This paper presents an eighth order low-pass filter which has characteristics of fault tolerance through the use of evolvable hardware (EHW). A field programmable analog array (FPAA) is used to implement the filter under study. The reconfiguration process of the filter involves the execution of a genetic algorithm (GA) in an external computer, after a fault is detected. To perform the test of the filter, we assume that a frequency response characterization test is used. A parametric fault model that considers deviations in the values of one of the capacitors or one of the input amplifiers (IA) is used to evaluate the performance of developed GA. The results show that GA finds filter configurations that meet the restrictions set for all the simulated faults. Additionally, this work shows better results compared to those previously obtained using another EHW scheme for the same low-pass filter.
publishDate 2013
dc.date.none.fl_str_mv 2013-09
dc.type.none.fl_str_mv info:eu-repo/semantics/conferenceObject
info:eu-repo/semantics/publishedVersion
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http://purl.org/coar/resource_type/c_5794
info:ar-repo/semantics/documentoDeConferencia
format conferenceObject
status_str publishedVersion
dc.identifier.none.fl_str_mv http://sedici.unlp.edu.ar/handle/10915/76858
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dc.language.none.fl_str_mv eng
language eng
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info:eu-repo/semantics/altIdentifier/issn/1850-2806
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by-nc-sa/4.0/
Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc-sa/4.0/
Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)
dc.format.none.fl_str_mv application/pdf
140-151
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repository.name.fl_str_mv SEDICI (UNLP) - Universidad Nacional de La Plata
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