Fuzzy logic controllers on chip

Autores
Acosta, Nelson; Simonelli, Daniel Horacio
Año de publicación
2002
Idioma
inglés
Tipo de recurso
documento de conferencia
Estado
versión publicada
Descripción
This paper analyzes a fuzzy logic (FL) oriented instruction set (micro)controller and their implementations on FIPSOC1. VHDL code is synthesized using a small portion of FIPSOC FPGA2. This circuits are used from the mP8051 FIPSOC built-in microcontroller to provide efficient arithmetic operations such as multipliers, dividers, minimums and maximums.
Eje: Sistemas de Tiempo Real
Red de Universidades con Carreras en Informática (RedUNCI)
Materia
Ciencias Informáticas
Real time
Fuzzy Logic Controllers
Chip
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/22072
Acceder
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oai_identifier_str oai:sedici.unlp.edu.ar:10915/22072
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repository_id_str 1329
network_name_str SEDICI (UNLP)
spelling Fuzzy logic controllers on chipAcosta, NelsonSimonelli, Daniel HoracioCiencias InformáticasReal timeFuzzy Logic ControllersChipThis paper analyzes a fuzzy logic (FL) oriented instruction set (micro)controller and their implementations on FIPSOC1. VHDL code is synthesized using a small portion of FIPSOC FPGA2. This circuits are used from the mP8051 FIPSOC built-in microcontroller to provide efficient arithmetic operations such as multipliers, dividers, minimums and maximums.Eje: Sistemas de Tiempo RealRed de Universidades con Carreras en Informática (RedUNCI)2002-05info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdf484-488http://sedici.unlp.edu.ar/handle/10915/22072enginfo:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-sa/2.5/ar/Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-03T10:27:43Zoai:sedici.unlp.edu.ar:10915/22072Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-03 10:27:43.508SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv Fuzzy logic controllers on chip
title Fuzzy logic controllers on chip
spellingShingle Fuzzy logic controllers on chip
Acosta, Nelson
Ciencias Informáticas
Real time
Fuzzy Logic Controllers
Chip
title_short Fuzzy logic controllers on chip
title_full Fuzzy logic controllers on chip
title_fullStr Fuzzy logic controllers on chip
title_full_unstemmed Fuzzy logic controllers on chip
title_sort Fuzzy logic controllers on chip
dc.creator.none.fl_str_mv Acosta, Nelson
Simonelli, Daniel Horacio
author Acosta, Nelson
author_facet Acosta, Nelson
Simonelli, Daniel Horacio
author_role author
author2 Simonelli, Daniel Horacio
author2_role author
dc.subject.none.fl_str_mv Ciencias Informáticas
Real time
Fuzzy Logic Controllers
Chip
topic Ciencias Informáticas
Real time
Fuzzy Logic Controllers
Chip
dc.description.none.fl_txt_mv This paper analyzes a fuzzy logic (FL) oriented instruction set (micro)controller and their implementations on FIPSOC1. VHDL code is synthesized using a small portion of FIPSOC FPGA2. This circuits are used from the mP8051 FIPSOC built-in microcontroller to provide efficient arithmetic operations such as multipliers, dividers, minimums and maximums.
Eje: Sistemas de Tiempo Real
Red de Universidades con Carreras en Informática (RedUNCI)
description This paper analyzes a fuzzy logic (FL) oriented instruction set (micro)controller and their implementations on FIPSOC1. VHDL code is synthesized using a small portion of FIPSOC FPGA2. This circuits are used from the mP8051 FIPSOC built-in microcontroller to provide efficient arithmetic operations such as multipliers, dividers, minimums and maximums.
publishDate 2002
dc.date.none.fl_str_mv 2002-05
dc.type.none.fl_str_mv info:eu-repo/semantics/conferenceObject
info:eu-repo/semantics/publishedVersion
Objeto de conferencia
http://purl.org/coar/resource_type/c_5794
info:ar-repo/semantics/documentoDeConferencia
format conferenceObject
status_str publishedVersion
dc.identifier.none.fl_str_mv http://sedici.unlp.edu.ar/handle/10915/22072
url http://sedici.unlp.edu.ar/handle/10915/22072
dc.language.none.fl_str_mv eng
language eng
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
dc.format.none.fl_str_mv application/pdf
484-488
dc.source.none.fl_str_mv reponame:SEDICI (UNLP)
instname:Universidad Nacional de La Plata
instacron:UNLP
reponame_str SEDICI (UNLP)
collection SEDICI (UNLP)
instname_str Universidad Nacional de La Plata
instacron_str UNLP
institution UNLP
repository.name.fl_str_mv SEDICI (UNLP) - Universidad Nacional de La Plata
repository.mail.fl_str_mv alira@sedici.unlp.edu.ar
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score 13.13397

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