Towards a field configurable non-homogeneous multiprocessors architecture
- Autores
- Jaquenod, Guillermo A.; Villagarcía Wanza, Horacio A.; De Giusti, Marisa Raquel
- Año de publicación
- 2001
- Idioma
- inglés
- Tipo de recurso
- documento de conferencia
- Estado
- versión publicada
- Descripción
- Standard microprocessors are generally designed to deal efficiently with different types of tasks; their general purpose architecture can lead to misuse of resources, creating a large gap between the computational efficiency of microprocessors and custom silicon. The ever increasing complexity of Field Programmable Logic devices is driving the industry to look for innovative System on a Chip solutions; using programmable logic, the whole design can be tuned to the application requirements. In this paper, under the acronym MPOC (Multiprocessors On a Chip) we propose some applicable ideas on multiprocessing embedded configurable architectures, targeting System on a Programmable Chip (SOPC) cost-effective designs. Using heterogeneous medium or low performance soft-core processors instead of a single high performance processor, and some standardized communication schemes to link these multiple processors, the “best” core can be chosen for each subtask using a computational efficiency criteria, and therefore improving silicon usage. System-level design is also considered: models of tasks and links, parameterized soft-core processors, and the use of a standard HDL for system description can lead to automatic generation of the final design.
Facultad de Ingeniería (FI) - Materia
-
Ingeniería
Informática
embedded multiprocessing
system-on-chip
distributed heterogeneous embedded system
programmable logic
IP cores
system-level design - Nivel de accesibilidad
- acceso abierto
- Condiciones de uso
- http://creativecommons.org/licenses/by/2.5/ar/
- Repositorio
- Institución
- Universidad Nacional de La Plata
- OAI Identificador
- oai:sedici.unlp.edu.ar:10915/27583
Ver los metadatos del registro completo
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Towards a field configurable non-homogeneous multiprocessors architectureJaquenod, Guillermo A.Villagarcía Wanza, Horacio A.De Giusti, Marisa RaquelIngenieríaInformáticaembedded multiprocessingsystem-on-chipdistributed heterogeneous embedded systemprogrammable logicIP coressystem-level designStandard microprocessors are generally designed to deal efficiently with different types of tasks; their general purpose architecture can lead to misuse of resources, creating a large gap between the computational efficiency of microprocessors and custom silicon. The ever increasing complexity of Field Programmable Logic devices is driving the industry to look for innovative System on a Chip solutions; using programmable logic, the whole design can be tuned to the application requirements. In this paper, under the acronym MPOC (Multiprocessors On a Chip) we propose some applicable ideas on multiprocessing embedded configurable architectures, targeting System on a Programmable Chip (SOPC) cost-effective designs. Using heterogeneous medium or low performance soft-core processors instead of a single high performance processor, and some standardized communication schemes to link these multiple processors, the “best” core can be chosen for each subtask using a computational efficiency criteria, and therefore improving silicon usage. System-level design is also considered: models of tasks and links, parameterized soft-core processors, and the use of a standard HDL for system description can lead to automatic generation of the final design.Facultad de Ingeniería (FI)2001info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdf248-253http://sedici.unlp.edu.ar/handle/10915/27583enginfo:eu-repo/semantics/altIdentifier/isbn/980-07-7529-3info:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by/2.5/ar/Creative Commons Attribution 2.5 Argentina (CC BY 2.5)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-29T10:56:52Zoai:sedici.unlp.edu.ar:10915/27583Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-29 10:56:53.185SEDICI (UNLP) - Universidad Nacional de La Platafalse |
dc.title.none.fl_str_mv |
Towards a field configurable non-homogeneous multiprocessors architecture |
title |
Towards a field configurable non-homogeneous multiprocessors architecture |
spellingShingle |
Towards a field configurable non-homogeneous multiprocessors architecture Jaquenod, Guillermo A. Ingeniería Informática embedded multiprocessing system-on-chip distributed heterogeneous embedded system programmable logic IP cores system-level design |
title_short |
Towards a field configurable non-homogeneous multiprocessors architecture |
title_full |
Towards a field configurable non-homogeneous multiprocessors architecture |
title_fullStr |
Towards a field configurable non-homogeneous multiprocessors architecture |
title_full_unstemmed |
Towards a field configurable non-homogeneous multiprocessors architecture |
title_sort |
Towards a field configurable non-homogeneous multiprocessors architecture |
dc.creator.none.fl_str_mv |
Jaquenod, Guillermo A. Villagarcía Wanza, Horacio A. De Giusti, Marisa Raquel |
author |
Jaquenod, Guillermo A. |
author_facet |
Jaquenod, Guillermo A. Villagarcía Wanza, Horacio A. De Giusti, Marisa Raquel |
author_role |
author |
author2 |
Villagarcía Wanza, Horacio A. De Giusti, Marisa Raquel |
author2_role |
author author |
dc.subject.none.fl_str_mv |
Ingeniería Informática embedded multiprocessing system-on-chip distributed heterogeneous embedded system programmable logic IP cores system-level design |
topic |
Ingeniería Informática embedded multiprocessing system-on-chip distributed heterogeneous embedded system programmable logic IP cores system-level design |
dc.description.none.fl_txt_mv |
Standard microprocessors are generally designed to deal efficiently with different types of tasks; their general purpose architecture can lead to misuse of resources, creating a large gap between the computational efficiency of microprocessors and custom silicon. The ever increasing complexity of Field Programmable Logic devices is driving the industry to look for innovative System on a Chip solutions; using programmable logic, the whole design can be tuned to the application requirements. In this paper, under the acronym MPOC (Multiprocessors On a Chip) we propose some applicable ideas on multiprocessing embedded configurable architectures, targeting System on a Programmable Chip (SOPC) cost-effective designs. Using heterogeneous medium or low performance soft-core processors instead of a single high performance processor, and some standardized communication schemes to link these multiple processors, the “best” core can be chosen for each subtask using a computational efficiency criteria, and therefore improving silicon usage. System-level design is also considered: models of tasks and links, parameterized soft-core processors, and the use of a standard HDL for system description can lead to automatic generation of the final design. Facultad de Ingeniería (FI) |
description |
Standard microprocessors are generally designed to deal efficiently with different types of tasks; their general purpose architecture can lead to misuse of resources, creating a large gap between the computational efficiency of microprocessors and custom silicon. The ever increasing complexity of Field Programmable Logic devices is driving the industry to look for innovative System on a Chip solutions; using programmable logic, the whole design can be tuned to the application requirements. In this paper, under the acronym MPOC (Multiprocessors On a Chip) we propose some applicable ideas on multiprocessing embedded configurable architectures, targeting System on a Programmable Chip (SOPC) cost-effective designs. Using heterogeneous medium or low performance soft-core processors instead of a single high performance processor, and some standardized communication schemes to link these multiple processors, the “best” core can be chosen for each subtask using a computational efficiency criteria, and therefore improving silicon usage. System-level design is also considered: models of tasks and links, parameterized soft-core processors, and the use of a standard HDL for system description can lead to automatic generation of the final design. |
publishDate |
2001 |
dc.date.none.fl_str_mv |
2001 |
dc.type.none.fl_str_mv |
info:eu-repo/semantics/conferenceObject info:eu-repo/semantics/publishedVersion Objeto de conferencia http://purl.org/coar/resource_type/c_5794 info:ar-repo/semantics/documentoDeConferencia |
format |
conferenceObject |
status_str |
publishedVersion |
dc.identifier.none.fl_str_mv |
http://sedici.unlp.edu.ar/handle/10915/27583 |
url |
http://sedici.unlp.edu.ar/handle/10915/27583 |
dc.language.none.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
info:eu-repo/semantics/altIdentifier/isbn/980-07-7529-3 |
dc.rights.none.fl_str_mv |
info:eu-repo/semantics/openAccess http://creativecommons.org/licenses/by/2.5/ar/ Creative Commons Attribution 2.5 Argentina (CC BY 2.5) |
eu_rights_str_mv |
openAccess |
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http://creativecommons.org/licenses/by/2.5/ar/ Creative Commons Attribution 2.5 Argentina (CC BY 2.5) |
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application/pdf 248-253 |
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reponame:SEDICI (UNLP) instname:Universidad Nacional de La Plata instacron:UNLP |
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SEDICI (UNLP) - Universidad Nacional de La Plata |
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