System on Chip based Brain-Computer Interface
- Autores
- García, Pablo Andrés; Oliva, Matías Javier; Spinelli, Enrique Mario
- Año de publicación
- 2020
- Idioma
- inglés
- Tipo de recurso
- documento de conferencia
- Estado
- versión publicada
- Descripción
- This work presents an autonomous embedded system based on a system on chip that implements a braincomputer interface. The brain-computer interface is based on steady-state visual evoked biopotential and the embedded system on a system on chip which combines a dual-core Cortex-A9 embedded processor with programmable logic for design flexibility. The programmable logic side provides a solution for parallel tasks with strict real-time constraints, and the processor includes capabilities to port an operating system with a graphical user interface, network support, and file system, among others. Initially, a verification of the operative system running on the embedded processor sharing data with the logic side is presented, to find out its real-time capability as a set. Finally, a brain-computer interface based on visual evoked potentials is implemented. Results of this application recovering visual evoked potential on the embedded system, are also presented.
Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales - Materia
-
Ingeniería Electrónica
Embedded system
System on chip
Assistive Device
Bran-computer Interface
Steady-State Visual Evoked Potential
Speller - Nivel de accesibilidad
- acceso abierto
- Condiciones de uso
- http://creativecommons.org/licenses/by-nc-nd/4.0/
- Repositorio
.jpg)
- Institución
- Universidad Nacional de La Plata
- OAI Identificador
- oai:sedici.unlp.edu.ar:10915/160821
Ver los metadatos del registro completo
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System on Chip based Brain-Computer InterfaceGarcía, Pablo AndrésOliva, Matías JavierSpinelli, Enrique MarioIngeniería ElectrónicaEmbedded systemSystem on chipAssistive DeviceBran-computer InterfaceSteady-State Visual Evoked PotentialSpellerThis work presents an autonomous embedded system based on a system on chip that implements a braincomputer interface. The brain-computer interface is based on steady-state visual evoked biopotential and the embedded system on a system on chip which combines a dual-core Cortex-A9 embedded processor with programmable logic for design flexibility. The programmable logic side provides a solution for parallel tasks with strict real-time constraints, and the processor includes capabilities to port an operating system with a graphical user interface, network support, and file system, among others. Initially, a verification of the operative system running on the embedded processor sharing data with the logic side is presented, to find out its real-time capability as a set. Finally, a brain-computer interface based on visual evoked potentials is implemented. Results of this application recovering visual evoked potential on the embedded system, are also presented.Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales2020-10-30info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdf47-52http://sedici.unlp.edu.ar/handle/10915/160821enginfo:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-nd/4.0/Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-10-22T17:23:03Zoai:sedici.unlp.edu.ar:10915/160821Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-10-22 17:23:03.345SEDICI (UNLP) - Universidad Nacional de La Platafalse |
| dc.title.none.fl_str_mv |
System on Chip based Brain-Computer Interface |
| title |
System on Chip based Brain-Computer Interface |
| spellingShingle |
System on Chip based Brain-Computer Interface García, Pablo Andrés Ingeniería Electrónica Embedded system System on chip Assistive Device Bran-computer Interface Steady-State Visual Evoked Potential Speller |
| title_short |
System on Chip based Brain-Computer Interface |
| title_full |
System on Chip based Brain-Computer Interface |
| title_fullStr |
System on Chip based Brain-Computer Interface |
| title_full_unstemmed |
System on Chip based Brain-Computer Interface |
| title_sort |
System on Chip based Brain-Computer Interface |
| dc.creator.none.fl_str_mv |
García, Pablo Andrés Oliva, Matías Javier Spinelli, Enrique Mario |
| author |
García, Pablo Andrés |
| author_facet |
García, Pablo Andrés Oliva, Matías Javier Spinelli, Enrique Mario |
| author_role |
author |
| author2 |
Oliva, Matías Javier Spinelli, Enrique Mario |
| author2_role |
author author |
| dc.subject.none.fl_str_mv |
Ingeniería Electrónica Embedded system System on chip Assistive Device Bran-computer Interface Steady-State Visual Evoked Potential Speller |
| topic |
Ingeniería Electrónica Embedded system System on chip Assistive Device Bran-computer Interface Steady-State Visual Evoked Potential Speller |
| dc.description.none.fl_txt_mv |
This work presents an autonomous embedded system based on a system on chip that implements a braincomputer interface. The brain-computer interface is based on steady-state visual evoked biopotential and the embedded system on a system on chip which combines a dual-core Cortex-A9 embedded processor with programmable logic for design flexibility. The programmable logic side provides a solution for parallel tasks with strict real-time constraints, and the processor includes capabilities to port an operating system with a graphical user interface, network support, and file system, among others. Initially, a verification of the operative system running on the embedded processor sharing data with the logic side is presented, to find out its real-time capability as a set. Finally, a brain-computer interface based on visual evoked potentials is implemented. Results of this application recovering visual evoked potential on the embedded system, are also presented. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales |
| description |
This work presents an autonomous embedded system based on a system on chip that implements a braincomputer interface. The brain-computer interface is based on steady-state visual evoked biopotential and the embedded system on a system on chip which combines a dual-core Cortex-A9 embedded processor with programmable logic for design flexibility. The programmable logic side provides a solution for parallel tasks with strict real-time constraints, and the processor includes capabilities to port an operating system with a graphical user interface, network support, and file system, among others. Initially, a verification of the operative system running on the embedded processor sharing data with the logic side is presented, to find out its real-time capability as a set. Finally, a brain-computer interface based on visual evoked potentials is implemented. Results of this application recovering visual evoked potential on the embedded system, are also presented. |
| publishDate |
2020 |
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2020-10-30 |
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info:eu-repo/semantics/conferenceObject info:eu-repo/semantics/publishedVersion Objeto de conferencia http://purl.org/coar/resource_type/c_5794 info:ar-repo/semantics/documentoDeConferencia |
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eng |
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