Towards a field configurable non-homogeneous multiprocessors architecture
- Autores
- Jaquenod, Guillermo A.; Villagarcía Wanza, Horacio Alfredo; De Giusti, Marisa Raquel
- Año de publicación
- 2001
- Idioma
- inglés
- Tipo de recurso
- documento de conferencia
- Estado
- versión publicada
- Descripción
- Standard microprocessors are generally designed to deal efficiently with different types of tasks; their general purpose architecture can lead to misuse of resources, creating a large gap between the computational efficiency of microprocessors and custom silicon. The ever increasing complexity of Field Programmable Logic devices is driving the industry to look for innovative System on a Chip solutions; using programmable logic, the whole design can be tuned to the application requirements. In this paper, under the acronym MPOC (Multiprocessors On a Chip) we propose some applicable ideas on multiprocessing embedded configurable architectures, targeting System on a Programmable Chip (SOPC) cost-effective designs. Using heterogeneous medium or low performance soft-core processors instead of a single high performance processor, and some standardized communication schemes to link these multiple processors, the “best” core can be chosen for each subtask using a computational efficiency criteria, and therefore improving silicon usage. System-level design is also considered: models of tasks and links, parameterized soft-core processors, and the use of a standard HDL for system description can lead to automatic generation of the final design.
- Materia
-
Ciencias de la Computación
embedded multiprocessing
system-on-chip
distributed heterogeneous embedded system
programmable logic
IP cores
system-level design - Nivel de accesibilidad
- acceso abierto
- Condiciones de uso
- http://creativecommons.org/licenses/by/4.0/
- Repositorio
- Institución
- Comisión de Investigaciones Científicas de la Provincia de Buenos Aires
- OAI Identificador
- oai:digital.cic.gba.gob.ar:11746/1546
Ver los metadatos del registro completo
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Towards a field configurable non-homogeneous multiprocessors architectureJaquenod, Guillermo A.Villagarcía Wanza, Horacio AlfredoDe Giusti, Marisa RaquelCiencias de la Computaciónembedded multiprocessingsystem-on-chipdistributed heterogeneous embedded systemprogrammable logicIP coressystem-level designStandard microprocessors are generally designed to deal efficiently with different types of tasks; their general purpose architecture can lead to misuse of resources, creating a large gap between the computational efficiency of microprocessors and custom silicon. The ever increasing complexity of Field Programmable Logic devices is driving the industry to look for innovative System on a Chip solutions; using programmable logic, the whole design can be tuned to the application requirements. In this paper, under the acronym MPOC (Multiprocessors On a Chip) we propose some applicable ideas on multiprocessing embedded configurable architectures, targeting System on a Programmable Chip (SOPC) cost-effective designs. Using heterogeneous medium or low performance soft-core processors instead of a single high performance processor, and some standardized communication schemes to link these multiple processors, the “best” core can be chosen for each subtask using a computational efficiency criteria, and therefore improving silicon usage. System-level design is also considered: models of tasks and links, parameterized soft-core processors, and the use of a standard HDL for system description can lead to automatic generation of the final design.2001info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionhttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdfhttps://digital.cic.gba.gob.ar/handle/11746/1546enghttp://digital.cic.gba.gob.ar/handle/123456789/1535info:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by/4.0/reponame:CIC Digital (CICBA)instname:Comisión de Investigaciones Científicas de la Provincia de Buenos Airesinstacron:CICBA2025-09-29T13:39:51Zoai:digital.cic.gba.gob.ar:11746/1546Institucionalhttp://digital.cic.gba.gob.arOrganismo científico-tecnológicoNo correspondehttp://digital.cic.gba.gob.ar/oai/snrdmarisa.degiusti@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:94412025-09-29 13:39:51.607CIC Digital (CICBA) - Comisión de Investigaciones Científicas de la Provincia de Buenos Airesfalse |
dc.title.none.fl_str_mv |
Towards a field configurable non-homogeneous multiprocessors architecture |
title |
Towards a field configurable non-homogeneous multiprocessors architecture |
spellingShingle |
Towards a field configurable non-homogeneous multiprocessors architecture Jaquenod, Guillermo A. Ciencias de la Computación embedded multiprocessing system-on-chip distributed heterogeneous embedded system programmable logic IP cores system-level design |
title_short |
Towards a field configurable non-homogeneous multiprocessors architecture |
title_full |
Towards a field configurable non-homogeneous multiprocessors architecture |
title_fullStr |
Towards a field configurable non-homogeneous multiprocessors architecture |
title_full_unstemmed |
Towards a field configurable non-homogeneous multiprocessors architecture |
title_sort |
Towards a field configurable non-homogeneous multiprocessors architecture |
dc.creator.none.fl_str_mv |
Jaquenod, Guillermo A. Villagarcía Wanza, Horacio Alfredo De Giusti, Marisa Raquel |
author |
Jaquenod, Guillermo A. |
author_facet |
Jaquenod, Guillermo A. Villagarcía Wanza, Horacio Alfredo De Giusti, Marisa Raquel |
author_role |
author |
author2 |
Villagarcía Wanza, Horacio Alfredo De Giusti, Marisa Raquel |
author2_role |
author author |
dc.subject.none.fl_str_mv |
Ciencias de la Computación embedded multiprocessing system-on-chip distributed heterogeneous embedded system programmable logic IP cores system-level design |
topic |
Ciencias de la Computación embedded multiprocessing system-on-chip distributed heterogeneous embedded system programmable logic IP cores system-level design |
dc.description.none.fl_txt_mv |
Standard microprocessors are generally designed to deal efficiently with different types of tasks; their general purpose architecture can lead to misuse of resources, creating a large gap between the computational efficiency of microprocessors and custom silicon. The ever increasing complexity of Field Programmable Logic devices is driving the industry to look for innovative System on a Chip solutions; using programmable logic, the whole design can be tuned to the application requirements. In this paper, under the acronym MPOC (Multiprocessors On a Chip) we propose some applicable ideas on multiprocessing embedded configurable architectures, targeting System on a Programmable Chip (SOPC) cost-effective designs. Using heterogeneous medium or low performance soft-core processors instead of a single high performance processor, and some standardized communication schemes to link these multiple processors, the “best” core can be chosen for each subtask using a computational efficiency criteria, and therefore improving silicon usage. System-level design is also considered: models of tasks and links, parameterized soft-core processors, and the use of a standard HDL for system description can lead to automatic generation of the final design. |
description |
Standard microprocessors are generally designed to deal efficiently with different types of tasks; their general purpose architecture can lead to misuse of resources, creating a large gap between the computational efficiency of microprocessors and custom silicon. The ever increasing complexity of Field Programmable Logic devices is driving the industry to look for innovative System on a Chip solutions; using programmable logic, the whole design can be tuned to the application requirements. In this paper, under the acronym MPOC (Multiprocessors On a Chip) we propose some applicable ideas on multiprocessing embedded configurable architectures, targeting System on a Programmable Chip (SOPC) cost-effective designs. Using heterogeneous medium or low performance soft-core processors instead of a single high performance processor, and some standardized communication schemes to link these multiple processors, the “best” core can be chosen for each subtask using a computational efficiency criteria, and therefore improving silicon usage. System-level design is also considered: models of tasks and links, parameterized soft-core processors, and the use of a standard HDL for system description can lead to automatic generation of the final design. |
publishDate |
2001 |
dc.date.none.fl_str_mv |
2001 |
dc.type.none.fl_str_mv |
info:eu-repo/semantics/conferenceObject info:eu-repo/semantics/publishedVersion http://purl.org/coar/resource_type/c_5794 info:ar-repo/semantics/documentoDeConferencia |
format |
conferenceObject |
status_str |
publishedVersion |
dc.identifier.none.fl_str_mv |
https://digital.cic.gba.gob.ar/handle/11746/1546 |
url |
https://digital.cic.gba.gob.ar/handle/11746/1546 |
dc.language.none.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
http://digital.cic.gba.gob.ar/handle/123456789/1535 |
dc.rights.none.fl_str_mv |
info:eu-repo/semantics/openAccess http://creativecommons.org/licenses/by/4.0/ |
eu_rights_str_mv |
openAccess |
rights_invalid_str_mv |
http://creativecommons.org/licenses/by/4.0/ |
dc.format.none.fl_str_mv |
application/pdf |
dc.source.none.fl_str_mv |
reponame:CIC Digital (CICBA) instname:Comisión de Investigaciones Científicas de la Provincia de Buenos Aires instacron:CICBA |
reponame_str |
CIC Digital (CICBA) |
collection |
CIC Digital (CICBA) |
instname_str |
Comisión de Investigaciones Científicas de la Provincia de Buenos Aires |
instacron_str |
CICBA |
institution |
CICBA |
repository.name.fl_str_mv |
CIC Digital (CICBA) - Comisión de Investigaciones Científicas de la Provincia de Buenos Aires |
repository.mail.fl_str_mv |
marisa.degiusti@sedici.unlp.edu.ar |
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1844618581359198208 |
score |
13.070432 |