Minimum area, low cost fpga implementation of aes
- Autores
- Liberatori, Mónica Cristina; Bonadero, Juan Carlos
- Año de publicación
- 2004
- Idioma
- inglés
- Tipo de recurso
- documento de conferencia
- Estado
- versión publicada
- Descripción
- The Rijndael cipher, designed by Joan Daemen and Vincent Rijmen and recently selected as the official Advanced Encryption Standard (AES) is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed. This paper presents an 8-bit FPGA implementation of the 128-bit block and 128 bit-key AES cipher. Selected FPGA Family is Altera Flex 10K. The cipher operates at 25 MHz and consumes 470 clock cycles for algorithm encryption, resulting in a throughput of 6.8 Mbps. The design target was optimisation of area and cost.
Eje: IV - Workshop de procesamiento distribuido y paralelo
Red de Universidades con Carreras en Informática (RedUNCI) - Materia
-
Ciencias Informáticas
Parallel processing
Distributed
AES
cipher
cryptography
FPGA
VHDL - Nivel de accesibilidad
- acceso abierto
- Condiciones de uso
- http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
- Repositorio
.jpg)
- Institución
- Universidad Nacional de La Plata
- OAI Identificador
- oai:sedici.unlp.edu.ar:10915/22492
Ver los metadatos del registro completo
| id |
SEDICI_23c15a3a7bb9cec6230ccd289b15fc25 |
|---|---|
| oai_identifier_str |
oai:sedici.unlp.edu.ar:10915/22492 |
| network_acronym_str |
SEDICI |
| repository_id_str |
1329 |
| network_name_str |
SEDICI (UNLP) |
| spelling |
Minimum area, low cost fpga implementation of aesLiberatori, Mónica CristinaBonadero, Juan CarlosCiencias InformáticasParallel processingDistributedAESciphercryptographyFPGAVHDLThe Rijndael cipher, designed by Joan Daemen and Vincent Rijmen and recently selected as the official Advanced Encryption Standard (AES) is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed. This paper presents an 8-bit FPGA implementation of the 128-bit block and 128 bit-key AES cipher. Selected FPGA Family is Altera Flex 10K. The cipher operates at 25 MHz and consumes 470 clock cycles for algorithm encryption, resulting in a throughput of 6.8 Mbps. The design target was optimisation of area and cost.Eje: IV - Workshop de procesamiento distribuido y paraleloRed de Universidades con Carreras en Informática (RedUNCI)2004info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdfhttp://sedici.unlp.edu.ar/handle/10915/22492enginfo:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-sa/2.5/ar/Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-29T10:55:02Zoai:sedici.unlp.edu.ar:10915/22492Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-29 10:55:03.247SEDICI (UNLP) - Universidad Nacional de La Platafalse |
| dc.title.none.fl_str_mv |
Minimum area, low cost fpga implementation of aes |
| title |
Minimum area, low cost fpga implementation of aes |
| spellingShingle |
Minimum area, low cost fpga implementation of aes Liberatori, Mónica Cristina Ciencias Informáticas Parallel processing Distributed AES cipher cryptography FPGA VHDL |
| title_short |
Minimum area, low cost fpga implementation of aes |
| title_full |
Minimum area, low cost fpga implementation of aes |
| title_fullStr |
Minimum area, low cost fpga implementation of aes |
| title_full_unstemmed |
Minimum area, low cost fpga implementation of aes |
| title_sort |
Minimum area, low cost fpga implementation of aes |
| dc.creator.none.fl_str_mv |
Liberatori, Mónica Cristina Bonadero, Juan Carlos |
| author |
Liberatori, Mónica Cristina |
| author_facet |
Liberatori, Mónica Cristina Bonadero, Juan Carlos |
| author_role |
author |
| author2 |
Bonadero, Juan Carlos |
| author2_role |
author |
| dc.subject.none.fl_str_mv |
Ciencias Informáticas Parallel processing Distributed AES cipher cryptography FPGA VHDL |
| topic |
Ciencias Informáticas Parallel processing Distributed AES cipher cryptography FPGA VHDL |
| dc.description.none.fl_txt_mv |
The Rijndael cipher, designed by Joan Daemen and Vincent Rijmen and recently selected as the official Advanced Encryption Standard (AES) is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed. This paper presents an 8-bit FPGA implementation of the 128-bit block and 128 bit-key AES cipher. Selected FPGA Family is Altera Flex 10K. The cipher operates at 25 MHz and consumes 470 clock cycles for algorithm encryption, resulting in a throughput of 6.8 Mbps. The design target was optimisation of area and cost. Eje: IV - Workshop de procesamiento distribuido y paralelo Red de Universidades con Carreras en Informática (RedUNCI) |
| description |
The Rijndael cipher, designed by Joan Daemen and Vincent Rijmen and recently selected as the official Advanced Encryption Standard (AES) is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed. This paper presents an 8-bit FPGA implementation of the 128-bit block and 128 bit-key AES cipher. Selected FPGA Family is Altera Flex 10K. The cipher operates at 25 MHz and consumes 470 clock cycles for algorithm encryption, resulting in a throughput of 6.8 Mbps. The design target was optimisation of area and cost. |
| publishDate |
2004 |
| dc.date.none.fl_str_mv |
2004 |
| dc.type.none.fl_str_mv |
info:eu-repo/semantics/conferenceObject info:eu-repo/semantics/publishedVersion Objeto de conferencia http://purl.org/coar/resource_type/c_5794 info:ar-repo/semantics/documentoDeConferencia |
| format |
conferenceObject |
| status_str |
publishedVersion |
| dc.identifier.none.fl_str_mv |
http://sedici.unlp.edu.ar/handle/10915/22492 |
| url |
http://sedici.unlp.edu.ar/handle/10915/22492 |
| dc.language.none.fl_str_mv |
eng |
| language |
eng |
| dc.rights.none.fl_str_mv |
info:eu-repo/semantics/openAccess http://creativecommons.org/licenses/by-nc-sa/2.5/ar/ Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5) |
| eu_rights_str_mv |
openAccess |
| rights_invalid_str_mv |
http://creativecommons.org/licenses/by-nc-sa/2.5/ar/ Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5) |
| dc.format.none.fl_str_mv |
application/pdf |
| dc.source.none.fl_str_mv |
reponame:SEDICI (UNLP) instname:Universidad Nacional de La Plata instacron:UNLP |
| reponame_str |
SEDICI (UNLP) |
| collection |
SEDICI (UNLP) |
| instname_str |
Universidad Nacional de La Plata |
| instacron_str |
UNLP |
| institution |
UNLP |
| repository.name.fl_str_mv |
SEDICI (UNLP) - Universidad Nacional de La Plata |
| repository.mail.fl_str_mv |
alira@sedici.unlp.edu.ar |
| _version_ |
1844615809500971008 |
| score |
13.069144 |