SCDVP: A Simplicial CNN Digital Visual Processor

Autores
Di Federico, Martin; Julian, Pedro Marcelo; Mandolesi, Pablo Sergio
Año de publicación
2014
Idioma
inglés
Tipo de recurso
artículo
Estado
versión publicada
Descripción
In this work we present a programmable and reconfigurable single instruction multiple data (SIMD) visual processor based on the S-CNN architecture, namely, the Simplicial CNN Digital Visual Processor (SCDVP), oriented to high-performance low-level image processing. The cells in the array have a selectable neighborhood configuration and several registers, which provide the chip with extended spatial and temporal processing capabilities, in particular optical flow. A prototype 64 × 64 cell chip with two program memories and a column adder was fabricated in a 90 nm technology, which running at 133 MHz delivers 105.5 GOPS. The calculation at the cell level is performed with time coded signals and the program memory is located outside the array. This produces a very efficient realization in terms of area: 53.8 GOPS per mm2, which outperforms all results reported so far. We show that even after normalization, to account for technology scaling, the proposed architecture is the most efficient among all reported digital processors. Computation performance to power ratio also exceeds all previous results with 817.8 GOPS/W. Experimental results of the working chip are reported.
Fil: Di Federico, Martin. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Bahía Blanca. Instituto de Investigación En Ingeniería Eléctrica; Argentina. Universidad Nacional del Sur. Departamento de Ingenieria Electrica y de Computadoras; Argentina. Provincia de Buenos Aires. Gobernación. Comisión de Investigaciones Científicas; Argentina
Fil: Julian, Pedro Marcelo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Bahía Blanca. Instituto de Investigación En Ingeniería Eléctrica; Argentina. Universidad Nacional del Sur. Departamento de Ingenieria Electrica y de Computadoras; Argentina. Provincia de Buenos Aires. Gobernación. Comisión de Investigaciones Científicas; Argentina
Fil: Mandolesi, Pablo Sergio. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Bahía Blanca. Instituto de Investigación En Ingeniería Eléctrica; Argentina. Universidad Nacional del Sur. Departamento de Ingenieria Electrica y de Computadoras; Argentina. Provincia de Buenos Aires. Gobernación. Comisión de Investigaciones Científicas; Argentina
Materia
Cellular Neural Networks
Simplicial Computation
Image Processing
Pixel Level Processing
Vision Chip
Asic
Piecewise Linear
Nivel de accesibilidad
acceso abierto
Condiciones de uso
https://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Repositorio
CONICET Digital (CONICET)
Institución
Consejo Nacional de Investigaciones Científicas y Técnicas
OAI Identificador
oai:ri.conicet.gov.ar:11336/11760
Acceder
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oai_identifier_str oai:ri.conicet.gov.ar:11336/11760
network_acronym_str CONICETDig
repository_id_str 3498
network_name_str CONICET Digital (CONICET)
spelling SCDVP: A Simplicial CNN Digital Visual ProcessorDi Federico, MartinJulian, Pedro MarceloMandolesi, Pablo SergioCellular Neural NetworksSimplicial ComputationImage ProcessingPixel Level ProcessingVision ChipAsicPiecewise Linearhttps://purl.org/becyt/ford/2.2https://purl.org/becyt/ford/2In this work we present a programmable and reconfigurable single instruction multiple data (SIMD) visual processor based on the S-CNN architecture, namely, the Simplicial CNN Digital Visual Processor (SCDVP), oriented to high-performance low-level image processing. The cells in the array have a selectable neighborhood configuration and several registers, which provide the chip with extended spatial and temporal processing capabilities, in particular optical flow. A prototype 64 × 64 cell chip with two program memories and a column adder was fabricated in a 90 nm technology, which running at 133 MHz delivers 105.5 GOPS. The calculation at the cell level is performed with time coded signals and the program memory is located outside the array. This produces a very efficient realization in terms of area: 53.8 GOPS per mm2, which outperforms all results reported so far. We show that even after normalization, to account for technology scaling, the proposed architecture is the most efficient among all reported digital processors. Computation performance to power ratio also exceeds all previous results with 817.8 GOPS/W. Experimental results of the working chip are reported.Fil: Di Federico, Martin. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Bahía Blanca. Instituto de Investigación En Ingeniería Eléctrica; Argentina. Universidad Nacional del Sur. Departamento de Ingenieria Electrica y de Computadoras; Argentina. Provincia de Buenos Aires. Gobernación. Comisión de Investigaciones Científicas; ArgentinaFil: Julian, Pedro Marcelo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Bahía Blanca. Instituto de Investigación En Ingeniería Eléctrica; Argentina. Universidad Nacional del Sur. Departamento de Ingenieria Electrica y de Computadoras; Argentina. Provincia de Buenos Aires. Gobernación. Comisión de Investigaciones Científicas; ArgentinaFil: Mandolesi, Pablo Sergio. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Bahía Blanca. Instituto de Investigación En Ingeniería Eléctrica; Argentina. Universidad Nacional del Sur. Departamento de Ingenieria Electrica y de Computadoras; Argentina. Provincia de Buenos Aires. Gobernación. Comisión de Investigaciones Científicas; ArgentinaInstitute Of Electrical And Electronics Engineers2014-07info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionhttp://purl.org/coar/resource_type/c_6501info:ar-repo/semantics/articuloapplication/pdfapplication/pdfapplication/pdfapplication/pdfhttp://hdl.handle.net/11336/11760Di Federico, Martin; Julian, Pedro Marcelo; Mandolesi, Pablo Sergio; SCDVP: A Simplicial CNN Digital Visual Processor; Institute Of Electrical And Electronics Engineers; Ieee Transactions On Circuits And Systems I-regular Papers; 61; 7; 7-2014; 1962-19691549-83281558-0806enginfo:eu-repo/semantics/altIdentifier/url/http://ieeexplore.ieee.org/document/6716069/info:eu-repo/semantics/altIdentifier/url/https://doi.org/10.1109/TCSI.2013.2295959info:eu-repo/semantics/openAccesshttps://creativecommons.org/licenses/by-nc-sa/2.5/ar/reponame:CONICET Digital (CONICET)instname:Consejo Nacional de Investigaciones Científicas y Técnicas2025-09-03T09:50:54Zoai:ri.conicet.gov.ar:11336/11760instacron:CONICETInstitucionalhttp://ri.conicet.gov.ar/Organismo científico-tecnológicoNo correspondehttp://ri.conicet.gov.ar/oai/requestdasensio@conicet.gov.ar; lcarlino@conicet.gov.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:34982025-09-03 09:50:54.703CONICET Digital (CONICET) - Consejo Nacional de Investigaciones Científicas y Técnicasfalse
dc.title.none.fl_str_mv SCDVP: A Simplicial CNN Digital Visual Processor
title SCDVP: A Simplicial CNN Digital Visual Processor
spellingShingle SCDVP: A Simplicial CNN Digital Visual Processor
Di Federico, Martin
Cellular Neural Networks
Simplicial Computation
Image Processing
Pixel Level Processing
Vision Chip
Asic
Piecewise Linear
title_short SCDVP: A Simplicial CNN Digital Visual Processor
title_full SCDVP: A Simplicial CNN Digital Visual Processor
title_fullStr SCDVP: A Simplicial CNN Digital Visual Processor
title_full_unstemmed SCDVP: A Simplicial CNN Digital Visual Processor
title_sort SCDVP: A Simplicial CNN Digital Visual Processor
dc.creator.none.fl_str_mv Di Federico, Martin
Julian, Pedro Marcelo
Mandolesi, Pablo Sergio
author Di Federico, Martin
author_facet Di Federico, Martin
Julian, Pedro Marcelo
Mandolesi, Pablo Sergio
author_role author
author2 Julian, Pedro Marcelo
Mandolesi, Pablo Sergio
author2_role author
author
dc.subject.none.fl_str_mv Cellular Neural Networks
Simplicial Computation
Image Processing
Pixel Level Processing
Vision Chip
Asic
Piecewise Linear
topic Cellular Neural Networks
Simplicial Computation
Image Processing
Pixel Level Processing
Vision Chip
Asic
Piecewise Linear
purl_subject.fl_str_mv https://purl.org/becyt/ford/2.2
https://purl.org/becyt/ford/2
dc.description.none.fl_txt_mv In this work we present a programmable and reconfigurable single instruction multiple data (SIMD) visual processor based on the S-CNN architecture, namely, the Simplicial CNN Digital Visual Processor (SCDVP), oriented to high-performance low-level image processing. The cells in the array have a selectable neighborhood configuration and several registers, which provide the chip with extended spatial and temporal processing capabilities, in particular optical flow. A prototype 64 × 64 cell chip with two program memories and a column adder was fabricated in a 90 nm technology, which running at 133 MHz delivers 105.5 GOPS. The calculation at the cell level is performed with time coded signals and the program memory is located outside the array. This produces a very efficient realization in terms of area: 53.8 GOPS per mm2, which outperforms all results reported so far. We show that even after normalization, to account for technology scaling, the proposed architecture is the most efficient among all reported digital processors. Computation performance to power ratio also exceeds all previous results with 817.8 GOPS/W. Experimental results of the working chip are reported.
Fil: Di Federico, Martin. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Bahía Blanca. Instituto de Investigación En Ingeniería Eléctrica; Argentina. Universidad Nacional del Sur. Departamento de Ingenieria Electrica y de Computadoras; Argentina. Provincia de Buenos Aires. Gobernación. Comisión de Investigaciones Científicas; Argentina
Fil: Julian, Pedro Marcelo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Bahía Blanca. Instituto de Investigación En Ingeniería Eléctrica; Argentina. Universidad Nacional del Sur. Departamento de Ingenieria Electrica y de Computadoras; Argentina. Provincia de Buenos Aires. Gobernación. Comisión de Investigaciones Científicas; Argentina
Fil: Mandolesi, Pablo Sergio. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Bahía Blanca. Instituto de Investigación En Ingeniería Eléctrica; Argentina. Universidad Nacional del Sur. Departamento de Ingenieria Electrica y de Computadoras; Argentina. Provincia de Buenos Aires. Gobernación. Comisión de Investigaciones Científicas; Argentina
description In this work we present a programmable and reconfigurable single instruction multiple data (SIMD) visual processor based on the S-CNN architecture, namely, the Simplicial CNN Digital Visual Processor (SCDVP), oriented to high-performance low-level image processing. The cells in the array have a selectable neighborhood configuration and several registers, which provide the chip with extended spatial and temporal processing capabilities, in particular optical flow. A prototype 64 × 64 cell chip with two program memories and a column adder was fabricated in a 90 nm technology, which running at 133 MHz delivers 105.5 GOPS. The calculation at the cell level is performed with time coded signals and the program memory is located outside the array. This produces a very efficient realization in terms of area: 53.8 GOPS per mm2, which outperforms all results reported so far. We show that even after normalization, to account for technology scaling, the proposed architecture is the most efficient among all reported digital processors. Computation performance to power ratio also exceeds all previous results with 817.8 GOPS/W. Experimental results of the working chip are reported.
publishDate 2014
dc.date.none.fl_str_mv 2014-07
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
http://purl.org/coar/resource_type/c_6501
info:ar-repo/semantics/articulo
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv http://hdl.handle.net/11336/11760
Di Federico, Martin; Julian, Pedro Marcelo; Mandolesi, Pablo Sergio; SCDVP: A Simplicial CNN Digital Visual Processor; Institute Of Electrical And Electronics Engineers; Ieee Transactions On Circuits And Systems I-regular Papers; 61; 7; 7-2014; 1962-1969
1549-8328
1558-0806
url http://hdl.handle.net/11336/11760
identifier_str_mv Di Federico, Martin; Julian, Pedro Marcelo; Mandolesi, Pablo Sergio; SCDVP: A Simplicial CNN Digital Visual Processor; Institute Of Electrical And Electronics Engineers; Ieee Transactions On Circuits And Systems I-regular Papers; 61; 7; 7-2014; 1962-1969
1549-8328
1558-0806
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv info:eu-repo/semantics/altIdentifier/url/http://ieeexplore.ieee.org/document/6716069/
info:eu-repo/semantics/altIdentifier/url/https://doi.org/10.1109/TCSI.2013.2295959
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
https://creativecommons.org/licenses/by-nc-sa/2.5/ar/
eu_rights_str_mv openAccess
rights_invalid_str_mv https://creativecommons.org/licenses/by-nc-sa/2.5/ar/
dc.format.none.fl_str_mv application/pdf
application/pdf
application/pdf
application/pdf
dc.publisher.none.fl_str_mv Institute Of Electrical And Electronics Engineers
publisher.none.fl_str_mv Institute Of Electrical And Electronics Engineers
dc.source.none.fl_str_mv reponame:CONICET Digital (CONICET)
instname:Consejo Nacional de Investigaciones Científicas y Técnicas
reponame_str CONICET Digital (CONICET)
collection CONICET Digital (CONICET)
instname_str Consejo Nacional de Investigaciones Científicas y Técnicas
repository.name.fl_str_mv CONICET Digital (CONICET) - Consejo Nacional de Investigaciones Científicas y Técnicas
repository.mail.fl_str_mv dasensio@conicet.gov.ar; lcarlino@conicet.gov.ar
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score 12.885934

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