Energy aware simplicial processor for embedded morphological visual processing in intelligent internet of things

Autores
Villemur, Martin; Julian, Pedro Marcelo; Andreou, Andreas
Año de publicación
2018
Idioma
inglés
Tipo de recurso
artículo
Estado
versión publicada
Descripción
This Letter presents the architecture implementation and testing of an single instruction multiple data (SIMD) processor for energy aware embedded morphological visual processing using the simplicial piece-wise linear approximation. The architecture comprises a linear array of 48 × 48 processing elements, each connected to an eight-neighbour clique operating on binary input and state data. The architecture is synthesised from a custom designed ultra low-voltage CMOS library and fabricated in a 55 nm CMOS technology. The chip is capable of dynamic voltage/frequency scaling with power supplies between 0.5 and 1.2 V. The fabricated chip achieves an overall performance of 293 TOPS/W with dynamic energy dissipation efficiency of 3.4 fJ per output operation at 0.6 V.
Fil: Villemur, Martin. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; Argentina
Fil: Julian, Pedro Marcelo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; Argentina
Fil: Andreou, Andreas. University Johns Hopkins; Estados Unidos
Materia
VLSI
Internet of Things
Neural chips
Nivel de accesibilidad
acceso abierto
Condiciones de uso
https://creativecommons.org/licenses/by-nc-nd/2.5/ar/
Repositorio
CONICET Digital (CONICET)
Institución
Consejo Nacional de Investigaciones Científicas y Técnicas
OAI Identificador
oai:ri.conicet.gov.ar:11336/86483
Acceder
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oai_identifier_str oai:ri.conicet.gov.ar:11336/86483
network_acronym_str CONICETDig
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network_name_str CONICET Digital (CONICET)
spelling Energy aware simplicial processor for embedded morphological visual processing in intelligent internet of thingsVillemur, MartinJulian, Pedro MarceloAndreou, AndreasVLSIInternet of ThingsNeural chipshttps://purl.org/becyt/ford/2.2https://purl.org/becyt/ford/2This Letter presents the architecture implementation and testing of an single instruction multiple data (SIMD) processor for energy aware embedded morphological visual processing using the simplicial piece-wise linear approximation. The architecture comprises a linear array of 48 × 48 processing elements, each connected to an eight-neighbour clique operating on binary input and state data. The architecture is synthesised from a custom designed ultra low-voltage CMOS library and fabricated in a 55 nm CMOS technology. The chip is capable of dynamic voltage/frequency scaling with power supplies between 0.5 and 1.2 V. The fabricated chip achieves an overall performance of 293 TOPS/W with dynamic energy dissipation efficiency of 3.4 fJ per output operation at 0.6 V.Fil: Villemur, Martin. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Julian, Pedro Marcelo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Andreou, Andreas. University Johns Hopkins; Estados UnidosInstitution of Engineering and Technology2018-04info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionhttp://purl.org/coar/resource_type/c_6501info:ar-repo/semantics/articuloapplication/pdfapplication/pdfhttp://hdl.handle.net/11336/86483Villemur, Martin; Julian, Pedro Marcelo; Andreou, Andreas; Energy aware simplicial processor for embedded morphological visual processing in intelligent internet of things; Institution of Engineering and Technology; Electronics Letters; 54; 7; 4-2018; 420-4220013-5194CONICET DigitalCONICETenginfo:eu-repo/semantics/altIdentifier/url/https://ieeexplore.ieee.org/document/8326382info:eu-repo/semantics/altIdentifier/doi/10.1049/el.2017.4738info:eu-repo/semantics/openAccesshttps://creativecommons.org/licenses/by-nc-nd/2.5/ar/reponame:CONICET Digital (CONICET)instname:Consejo Nacional de Investigaciones Científicas y Técnicas2025-09-03T09:53:48Zoai:ri.conicet.gov.ar:11336/86483instacron:CONICETInstitucionalhttp://ri.conicet.gov.ar/Organismo científico-tecnológicoNo correspondehttp://ri.conicet.gov.ar/oai/requestdasensio@conicet.gov.ar; lcarlino@conicet.gov.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:34982025-09-03 09:53:49.093CONICET Digital (CONICET) - Consejo Nacional de Investigaciones Científicas y Técnicasfalse
dc.title.none.fl_str_mv Energy aware simplicial processor for embedded morphological visual processing in intelligent internet of things
title Energy aware simplicial processor for embedded morphological visual processing in intelligent internet of things
spellingShingle Energy aware simplicial processor for embedded morphological visual processing in intelligent internet of things
Villemur, Martin
VLSI
Internet of Things
Neural chips
title_short Energy aware simplicial processor for embedded morphological visual processing in intelligent internet of things
title_full Energy aware simplicial processor for embedded morphological visual processing in intelligent internet of things
title_fullStr Energy aware simplicial processor for embedded morphological visual processing in intelligent internet of things
title_full_unstemmed Energy aware simplicial processor for embedded morphological visual processing in intelligent internet of things
title_sort Energy aware simplicial processor for embedded morphological visual processing in intelligent internet of things
dc.creator.none.fl_str_mv Villemur, Martin
Julian, Pedro Marcelo
Andreou, Andreas
author Villemur, Martin
author_facet Villemur, Martin
Julian, Pedro Marcelo
Andreou, Andreas
author_role author
author2 Julian, Pedro Marcelo
Andreou, Andreas
author2_role author
author
dc.subject.none.fl_str_mv VLSI
Internet of Things
Neural chips
topic VLSI
Internet of Things
Neural chips
purl_subject.fl_str_mv https://purl.org/becyt/ford/2.2
https://purl.org/becyt/ford/2
dc.description.none.fl_txt_mv This Letter presents the architecture implementation and testing of an single instruction multiple data (SIMD) processor for energy aware embedded morphological visual processing using the simplicial piece-wise linear approximation. The architecture comprises a linear array of 48 × 48 processing elements, each connected to an eight-neighbour clique operating on binary input and state data. The architecture is synthesised from a custom designed ultra low-voltage CMOS library and fabricated in a 55 nm CMOS technology. The chip is capable of dynamic voltage/frequency scaling with power supplies between 0.5 and 1.2 V. The fabricated chip achieves an overall performance of 293 TOPS/W with dynamic energy dissipation efficiency of 3.4 fJ per output operation at 0.6 V.
Fil: Villemur, Martin. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; Argentina
Fil: Julian, Pedro Marcelo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; Argentina
Fil: Andreou, Andreas. University Johns Hopkins; Estados Unidos
description This Letter presents the architecture implementation and testing of an single instruction multiple data (SIMD) processor for energy aware embedded morphological visual processing using the simplicial piece-wise linear approximation. The architecture comprises a linear array of 48 × 48 processing elements, each connected to an eight-neighbour clique operating on binary input and state data. The architecture is synthesised from a custom designed ultra low-voltage CMOS library and fabricated in a 55 nm CMOS technology. The chip is capable of dynamic voltage/frequency scaling with power supplies between 0.5 and 1.2 V. The fabricated chip achieves an overall performance of 293 TOPS/W with dynamic energy dissipation efficiency of 3.4 fJ per output operation at 0.6 V.
publishDate 2018
dc.date.none.fl_str_mv 2018-04
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
http://purl.org/coar/resource_type/c_6501
info:ar-repo/semantics/articulo
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv http://hdl.handle.net/11336/86483
Villemur, Martin; Julian, Pedro Marcelo; Andreou, Andreas; Energy aware simplicial processor for embedded morphological visual processing in intelligent internet of things; Institution of Engineering and Technology; Electronics Letters; 54; 7; 4-2018; 420-422
0013-5194
CONICET Digital
CONICET
url http://hdl.handle.net/11336/86483
identifier_str_mv Villemur, Martin; Julian, Pedro Marcelo; Andreou, Andreas; Energy aware simplicial processor for embedded morphological visual processing in intelligent internet of things; Institution of Engineering and Technology; Electronics Letters; 54; 7; 4-2018; 420-422
0013-5194
CONICET Digital
CONICET
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv info:eu-repo/semantics/altIdentifier/url/https://ieeexplore.ieee.org/document/8326382
info:eu-repo/semantics/altIdentifier/doi/10.1049/el.2017.4738
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
https://creativecommons.org/licenses/by-nc-nd/2.5/ar/
eu_rights_str_mv openAccess
rights_invalid_str_mv https://creativecommons.org/licenses/by-nc-nd/2.5/ar/
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv Institution of Engineering and Technology
publisher.none.fl_str_mv Institution of Engineering and Technology
dc.source.none.fl_str_mv reponame:CONICET Digital (CONICET)
instname:Consejo Nacional de Investigaciones Científicas y Técnicas
reponame_str CONICET Digital (CONICET)
collection CONICET Digital (CONICET)
instname_str Consejo Nacional de Investigaciones Científicas y Técnicas
repository.name.fl_str_mv CONICET Digital (CONICET) - Consejo Nacional de Investigaciones Científicas y Técnicas
repository.mail.fl_str_mv dasensio@conicet.gov.ar; lcarlino@conicet.gov.ar
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score 13.13397

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