A low cost advance encryption standard (AES) co-processor implementation

Autores
Hernandez, Orlando J.; Sodon, Thomas; Adel, Michael; Kupp, Nathan
Año de publicación
2008
Idioma
inglés
Tipo de recurso
artículo
Estado
versión publicada
Descripción
The need for privacy has become a major priority for both governments and civilians desiring protection from signal interception. Widespread use of personal communications devices has only increased demand for a level of security on previously insecure communications. This paper presents a novel low-cost architecture for the Advanced Encryption Standard (AES) algorithm utilizing a field programmable gate array (FPGA). In as much as possible, this architecture uses a bit-serial approach, and it is also suitable for VLSI implementations. In this implementation, the primary objective was not to increase throughput or decrease latency, but to balance these factors in order to lower the cost. A focus on low cost resulted in a design well-suited for SoC implementations. This allows for scaling of the architecture towards vulnerable portable and cost-sensitive communications devices in consumer and military applications.
Facultad de Informática
Materia
Ciencias Informáticas
Cryptographic controls
FPGA Design
VLSI Design
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by-nc/3.0/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/9617

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network_name_str SEDICI (UNLP)
spelling A low cost advance encryption standard (AES) co-processor implementationHernandez, Orlando J.Sodon, ThomasAdel, MichaelKupp, NathanCiencias InformáticasCryptographic controlsFPGA DesignVLSI DesignThe need for privacy has become a major priority for both governments and civilians desiring protection from signal interception. Widespread use of personal communications devices has only increased demand for a level of security on previously insecure communications. This paper presents a novel low-cost architecture for the Advanced Encryption Standard (AES) algorithm utilizing a field programmable gate array (FPGA). In as much as possible, this architecture uses a bit-serial approach, and it is also suitable for VLSI implementations. In this implementation, the primary objective was not to increase throughput or decrease latency, but to balance these factors in order to lower the cost. A focus on low cost resulted in a design well-suited for SoC implementations. This allows for scaling of the architecture towards vulnerable portable and cost-sensitive communications devices in consumer and military applications.Facultad de Informática2008-04info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionArticulohttp://purl.org/coar/resource_type/c_6501info:ar-repo/semantics/articuloapplication/pdf8-14http://sedici.unlp.edu.ar/handle/10915/9617enginfo:eu-repo/semantics/altIdentifier/url/http://journal.info.unlp.edu.ar/wp-content/uploads/JCST-Apr08-2.pdfinfo:eu-repo/semantics/altIdentifier/issn/1666-6038info:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc/3.0/Creative Commons Attribution-NonCommercial 3.0 Unported (CC BY-NC 3.0)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-03T10:23:35Zoai:sedici.unlp.edu.ar:10915/9617Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-03 10:23:35.438SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv A low cost advance encryption standard (AES) co-processor implementation
title A low cost advance encryption standard (AES) co-processor implementation
spellingShingle A low cost advance encryption standard (AES) co-processor implementation
Hernandez, Orlando J.
Ciencias Informáticas
Cryptographic controls
FPGA Design
VLSI Design
title_short A low cost advance encryption standard (AES) co-processor implementation
title_full A low cost advance encryption standard (AES) co-processor implementation
title_fullStr A low cost advance encryption standard (AES) co-processor implementation
title_full_unstemmed A low cost advance encryption standard (AES) co-processor implementation
title_sort A low cost advance encryption standard (AES) co-processor implementation
dc.creator.none.fl_str_mv Hernandez, Orlando J.
Sodon, Thomas
Adel, Michael
Kupp, Nathan
author Hernandez, Orlando J.
author_facet Hernandez, Orlando J.
Sodon, Thomas
Adel, Michael
Kupp, Nathan
author_role author
author2 Sodon, Thomas
Adel, Michael
Kupp, Nathan
author2_role author
author
author
dc.subject.none.fl_str_mv Ciencias Informáticas
Cryptographic controls
FPGA Design
VLSI Design
topic Ciencias Informáticas
Cryptographic controls
FPGA Design
VLSI Design
dc.description.none.fl_txt_mv The need for privacy has become a major priority for both governments and civilians desiring protection from signal interception. Widespread use of personal communications devices has only increased demand for a level of security on previously insecure communications. This paper presents a novel low-cost architecture for the Advanced Encryption Standard (AES) algorithm utilizing a field programmable gate array (FPGA). In as much as possible, this architecture uses a bit-serial approach, and it is also suitable for VLSI implementations. In this implementation, the primary objective was not to increase throughput or decrease latency, but to balance these factors in order to lower the cost. A focus on low cost resulted in a design well-suited for SoC implementations. This allows for scaling of the architecture towards vulnerable portable and cost-sensitive communications devices in consumer and military applications.
Facultad de Informática
description The need for privacy has become a major priority for both governments and civilians desiring protection from signal interception. Widespread use of personal communications devices has only increased demand for a level of security on previously insecure communications. This paper presents a novel low-cost architecture for the Advanced Encryption Standard (AES) algorithm utilizing a field programmable gate array (FPGA). In as much as possible, this architecture uses a bit-serial approach, and it is also suitable for VLSI implementations. In this implementation, the primary objective was not to increase throughput or decrease latency, but to balance these factors in order to lower the cost. A focus on low cost resulted in a design well-suited for SoC implementations. This allows for scaling of the architecture towards vulnerable portable and cost-sensitive communications devices in consumer and military applications.
publishDate 2008
dc.date.none.fl_str_mv 2008-04
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
Articulo
http://purl.org/coar/resource_type/c_6501
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format article
status_str publishedVersion
dc.identifier.none.fl_str_mv http://sedici.unlp.edu.ar/handle/10915/9617
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dc.language.none.fl_str_mv eng
language eng
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info:eu-repo/semantics/altIdentifier/issn/1666-6038
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by-nc/3.0/
Creative Commons Attribution-NonCommercial 3.0 Unported (CC BY-NC 3.0)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc/3.0/
Creative Commons Attribution-NonCommercial 3.0 Unported (CC BY-NC 3.0)
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instname:Universidad Nacional de La Plata
instacron:UNLP
reponame_str SEDICI (UNLP)
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institution UNLP
repository.name.fl_str_mv SEDICI (UNLP) - Universidad Nacional de La Plata
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