CFD Solvers with Minimal Memory Access

Autores
Löhner, Rainald
Año de publicación
2017
Idioma
inglés
Tipo de recurso
documento de conferencia
Estado
versión publicada
Descripción
Many state of the art CFD codes that exhibit low computational intensity (flops per RAM access) "saturate" the memory bandwidth of modern chips after only a few cores, thus minimizing any benefits from going to a higher number of available cores. This bottleneck is expected to become even more pronounced for future manycore systems. This has led to the quest for CFD solvers with minimal memory access. We report on recent developments and results for Finite Difference and Edge-Based Finite Element solvers. The best of these implementations yield one residual for only 6 fetches and 4 stores, regardless of the size of the stencil (and therefore the discretization order). This means that in terms of memory access they are competitive even with finite difference stencils as low as 2 (typical of CFD codes with 2nd order spatial discretization of fluxes and 4th order damping). Timings for a low Mach number finite difference code using a 6th order spatial discretization show competitive timings as compared to conventional loops. This bodes well for future HPC architectures.
Publicado en: Mecánica Computacional vol. XXXV, no. 1.
Facultad de Ingeniería
Materia
Ingeniería
CFD codes
Memory bandwidth
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by-nc-sa/4.0/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/94120

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spelling CFD Solvers with Minimal Memory AccessLöhner, RainaldIngenieríaCFD codesMemory bandwidthMany state of the art CFD codes that exhibit low computational intensity (flops per RAM access) "saturate" the memory bandwidth of modern chips after only a few cores, thus minimizing any benefits from going to a higher number of available cores. This bottleneck is expected to become even more pronounced for future manycore systems. This has led to the quest for CFD solvers with minimal memory access. We report on recent developments and results for Finite Difference and Edge-Based Finite Element solvers. The best of these implementations yield one residual for only 6 fetches and 4 stores, regardless of the size of the stencil (and therefore the discretization order). This means that in terms of memory access they are competitive even with finite difference stencils as low as 2 (typical of CFD codes with 2nd order spatial discretization of fluxes and 4th order damping). Timings for a low Mach number finite difference code using a 6th order spatial discretization show competitive timings as compared to conventional loops. This bodes well for future HPC architectures.Publicado en: <i>Mecánica Computacional</i> vol. XXXV, no. 1.Facultad de Ingeniería2017-11info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionResumenhttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdf9http://sedici.unlp.edu.ar/handle/10915/94120enginfo:eu-repo/semantics/altIdentifier/url/https://cimec.org.ar/ojs/index.php/mc/article/view/5230info:eu-repo/semantics/altIdentifier/issn/2591-3522info:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-sa/4.0/Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-29T11:19:36Zoai:sedici.unlp.edu.ar:10915/94120Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-29 11:19:36.681SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv CFD Solvers with Minimal Memory Access
title CFD Solvers with Minimal Memory Access
spellingShingle CFD Solvers with Minimal Memory Access
Löhner, Rainald
Ingeniería
CFD codes
Memory bandwidth
title_short CFD Solvers with Minimal Memory Access
title_full CFD Solvers with Minimal Memory Access
title_fullStr CFD Solvers with Minimal Memory Access
title_full_unstemmed CFD Solvers with Minimal Memory Access
title_sort CFD Solvers with Minimal Memory Access
dc.creator.none.fl_str_mv Löhner, Rainald
author Löhner, Rainald
author_facet Löhner, Rainald
author_role author
dc.subject.none.fl_str_mv Ingeniería
CFD codes
Memory bandwidth
topic Ingeniería
CFD codes
Memory bandwidth
dc.description.none.fl_txt_mv Many state of the art CFD codes that exhibit low computational intensity (flops per RAM access) "saturate" the memory bandwidth of modern chips after only a few cores, thus minimizing any benefits from going to a higher number of available cores. This bottleneck is expected to become even more pronounced for future manycore systems. This has led to the quest for CFD solvers with minimal memory access. We report on recent developments and results for Finite Difference and Edge-Based Finite Element solvers. The best of these implementations yield one residual for only 6 fetches and 4 stores, regardless of the size of the stencil (and therefore the discretization order). This means that in terms of memory access they are competitive even with finite difference stencils as low as 2 (typical of CFD codes with 2nd order spatial discretization of fluxes and 4th order damping). Timings for a low Mach number finite difference code using a 6th order spatial discretization show competitive timings as compared to conventional loops. This bodes well for future HPC architectures.
Publicado en: <i>Mecánica Computacional</i> vol. XXXV, no. 1.
Facultad de Ingeniería
description Many state of the art CFD codes that exhibit low computational intensity (flops per RAM access) "saturate" the memory bandwidth of modern chips after only a few cores, thus minimizing any benefits from going to a higher number of available cores. This bottleneck is expected to become even more pronounced for future manycore systems. This has led to the quest for CFD solvers with minimal memory access. We report on recent developments and results for Finite Difference and Edge-Based Finite Element solvers. The best of these implementations yield one residual for only 6 fetches and 4 stores, regardless of the size of the stencil (and therefore the discretization order). This means that in terms of memory access they are competitive even with finite difference stencils as low as 2 (typical of CFD codes with 2nd order spatial discretization of fluxes and 4th order damping). Timings for a low Mach number finite difference code using a 6th order spatial discretization show competitive timings as compared to conventional loops. This bodes well for future HPC architectures.
publishDate 2017
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dc.language.none.fl_str_mv eng
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