Error detection techniques applicable in an architecture framework and design methodology for autonomic SoCs

Autores
Bouajila, Abdelmajid; Bernauer, Andreas; Herkersdorf, Andreas; Rosenstiel, Wolfgang; Bringmann, Oliver
Año de publicación
2006
Idioma
inglés
Tipo de recurso
documento de conferencia
Estado
versión publicada
Descripción
This work-in-progress paper surveys error detection techniques for transient, timing, permanent and logical errors in system-on-chip (SoC) design and discusses their applicability in the design of monitors for our Autonomic SoC architecture framework. These monitors will be needed to deliver necessary signals to achieve fault-tolerance, self-healing and self-calibration in our Autonomic SoC architecture. The framework combines the monitors with a welltailored design methodology that explores how the Autonomic SoC (ASoC) can cope with malfunctioning subcomponents.
1st IFIP International Conference on Biologically Inspired Cooperative Computing - Chip-Design
Red de Universidades con Carreras en Informática (RedUNCI)
Materia
Ciencias Informáticas
Error
system-on-chip (SoC)
error detection techniques
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/24005
Acceder
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oai_identifier_str oai:sedici.unlp.edu.ar:10915/24005
network_acronym_str SEDICI
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network_name_str SEDICI (UNLP)
spelling Error detection techniques applicable in an architecture framework and design methodology for autonomic SoCsBouajila, AbdelmajidBernauer, AndreasHerkersdorf, AndreasRosenstiel, WolfgangBringmann, OliverCiencias InformáticasErrorsystem-on-chip (SoC)error detection techniquesThis work-in-progress paper surveys error detection techniques for transient, timing, permanent and logical errors in system-on-chip (SoC) design and discusses their applicability in the design of monitors for our Autonomic SoC architecture framework. These monitors will be needed to deliver necessary signals to achieve fault-tolerance, self-healing and self-calibration in our Autonomic SoC architecture. The framework combines the monitors with a welltailored design methodology that explores how the Autonomic SoC (ASoC) can cope with malfunctioning subcomponents.1st IFIP International Conference on Biologically Inspired Cooperative Computing - Chip-DesignRed de Universidades con Carreras en Informática (RedUNCI)2006-08info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdfhttp://sedici.unlp.edu.ar/handle/10915/24005enginfo:eu-repo/semantics/altIdentifier/isbn/0-387-34632-5info:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-sa/2.5/ar/Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-29T10:55:41Zoai:sedici.unlp.edu.ar:10915/24005Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-29 10:55:41.369SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv Error detection techniques applicable in an architecture framework and design methodology for autonomic SoCs
title Error detection techniques applicable in an architecture framework and design methodology for autonomic SoCs
spellingShingle Error detection techniques applicable in an architecture framework and design methodology for autonomic SoCs
Bouajila, Abdelmajid
Ciencias Informáticas
Error
system-on-chip (SoC)
error detection techniques
title_short Error detection techniques applicable in an architecture framework and design methodology for autonomic SoCs
title_full Error detection techniques applicable in an architecture framework and design methodology for autonomic SoCs
title_fullStr Error detection techniques applicable in an architecture framework and design methodology for autonomic SoCs
title_full_unstemmed Error detection techniques applicable in an architecture framework and design methodology for autonomic SoCs
title_sort Error detection techniques applicable in an architecture framework and design methodology for autonomic SoCs
dc.creator.none.fl_str_mv Bouajila, Abdelmajid
Bernauer, Andreas
Herkersdorf, Andreas
Rosenstiel, Wolfgang
Bringmann, Oliver
author Bouajila, Abdelmajid
author_facet Bouajila, Abdelmajid
Bernauer, Andreas
Herkersdorf, Andreas
Rosenstiel, Wolfgang
Bringmann, Oliver
author_role author
author2 Bernauer, Andreas
Herkersdorf, Andreas
Rosenstiel, Wolfgang
Bringmann, Oliver
author2_role author
author
author
author
dc.subject.none.fl_str_mv Ciencias Informáticas
Error
system-on-chip (SoC)
error detection techniques
topic Ciencias Informáticas
Error
system-on-chip (SoC)
error detection techniques
dc.description.none.fl_txt_mv This work-in-progress paper surveys error detection techniques for transient, timing, permanent and logical errors in system-on-chip (SoC) design and discusses their applicability in the design of monitors for our Autonomic SoC architecture framework. These monitors will be needed to deliver necessary signals to achieve fault-tolerance, self-healing and self-calibration in our Autonomic SoC architecture. The framework combines the monitors with a welltailored design methodology that explores how the Autonomic SoC (ASoC) can cope with malfunctioning subcomponents.
1st IFIP International Conference on Biologically Inspired Cooperative Computing - Chip-Design
Red de Universidades con Carreras en Informática (RedUNCI)
description This work-in-progress paper surveys error detection techniques for transient, timing, permanent and logical errors in system-on-chip (SoC) design and discusses their applicability in the design of monitors for our Autonomic SoC architecture framework. These monitors will be needed to deliver necessary signals to achieve fault-tolerance, self-healing and self-calibration in our Autonomic SoC architecture. The framework combines the monitors with a welltailored design methodology that explores how the Autonomic SoC (ASoC) can cope with malfunctioning subcomponents.
publishDate 2006
dc.date.none.fl_str_mv 2006-08
dc.type.none.fl_str_mv info:eu-repo/semantics/conferenceObject
info:eu-repo/semantics/publishedVersion
Objeto de conferencia
http://purl.org/coar/resource_type/c_5794
info:ar-repo/semantics/documentoDeConferencia
format conferenceObject
status_str publishedVersion
dc.identifier.none.fl_str_mv http://sedici.unlp.edu.ar/handle/10915/24005
url http://sedici.unlp.edu.ar/handle/10915/24005
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv info:eu-repo/semantics/altIdentifier/isbn/0-387-34632-5
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:SEDICI (UNLP)
instname:Universidad Nacional de La Plata
instacron:UNLP
reponame_str SEDICI (UNLP)
collection SEDICI (UNLP)
instname_str Universidad Nacional de La Plata
instacron_str UNLP
institution UNLP
repository.name.fl_str_mv SEDICI (UNLP) - Universidad Nacional de La Plata
repository.mail.fl_str_mv alira@sedici.unlp.edu.ar
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