Exploring the Throughput-Fairness Trade-off on Asymmetric Multicore Systems

Autores
Saez, Juan Carlos; Pousa, Adrián; Castro, Fernando; Chaver, Daniel; Prieto-Matias, Manuel
Año de publicación
2014
Idioma
español castellano
Tipo de recurso
documento de conferencia
Estado
versión publicada
Descripción
Symmetric-ISA (instruction set architecture) asymmetric-performance multicore processors (AMPs) were shown to deliver higher performance per watt and area than symmetric CMPs (Chip Multi-Processors). Previous work has shown that this potential of AMP systems can be realizable thanks to the OS scheduler. Existing scheduling schemes that deliver fairness and priority enforcement on AMPs do not cater to the fact that applications in a multiprogram workload may derive different benefit from using fast cores in the system. As a result, they are likely to perform thread-to-core mappings that degrade the system throughput. To address this limitation, we propose Prop-SP, a scheduling algorithm that aims to improve the throughput-fairness trade-off on AMPs. Our evaluation on real hardware, and using scheduler implementations on a general-purpose OS, reveals that Prop-SP delivers a better throughput-fairness trade-off than state-of-the-art schedulers for a wide variety of multi-application workloads.
Publicado en Lecture Notes in Computer Science book series (LNCS, volume 8806)
Instituto de Investigación en Informática
Materia
Informática
asymmetric multicore
Scheduling
Operating systems
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by/4.0/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/132853
Acceder
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network_name_str SEDICI (UNLP)
spelling Exploring the Throughput-Fairness Trade-off on Asymmetric Multicore SystemsSaez, Juan CarlosPousa, AdriánCastro, FernandoChaver, DanielPrieto-Matias, ManuelInformáticaasymmetric multicoreSchedulingOperating systemsSymmetric-ISA (instruction set architecture) asymmetric-performance multicore processors (AMPs) were shown to deliver higher performance per watt and area than symmetric CMPs (Chip Multi-Processors). Previous work has shown that this potential of AMP systems can be realizable thanks to the OS scheduler. Existing scheduling schemes that deliver fairness and priority enforcement on AMPs do not cater to the fact that applications in a multiprogram workload may derive different benefit from using fast cores in the system. As a result, they are likely to perform thread-to-core mappings that degrade the system throughput. To address this limitation, we propose Prop-SP, a scheduling algorithm that aims to improve the throughput-fairness trade-off on AMPs. Our evaluation on real hardware, and using scheduler implementations on a general-purpose OS, reveals that Prop-SP delivers a better throughput-fairness trade-off than state-of-the-art schedulers for a wide variety of multi-application workloads.Publicado en <i>Lecture Notes in Computer Science</i> book series (LNCS, volume 8806)Instituto de Investigación en Informática2014info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdf326-337http://sedici.unlp.edu.ar/handle/10915/132853spainfo:eu-repo/semantics/altIdentifier/isbn/978-3-319-14312-5 978-3-319-14313-2info:eu-repo/semantics/altIdentifier/issn/0302-9743info:eu-repo/semantics/altIdentifier/issn/1611-3349info:eu-repo/semantics/altIdentifier/doi/10.1007/978-3-319-14313-2_28info:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by/4.0/Creative Commons Attribution 4.0 International (CC BY 4.0)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-10-15T11:24:29Zoai:sedici.unlp.edu.ar:10915/132853Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-10-15 11:24:30.259SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv Exploring the Throughput-Fairness Trade-off on Asymmetric Multicore Systems
title Exploring the Throughput-Fairness Trade-off on Asymmetric Multicore Systems
spellingShingle Exploring the Throughput-Fairness Trade-off on Asymmetric Multicore Systems
Saez, Juan Carlos
Informática
asymmetric multicore
Scheduling
Operating systems
title_short Exploring the Throughput-Fairness Trade-off on Asymmetric Multicore Systems
title_full Exploring the Throughput-Fairness Trade-off on Asymmetric Multicore Systems
title_fullStr Exploring the Throughput-Fairness Trade-off on Asymmetric Multicore Systems
title_full_unstemmed Exploring the Throughput-Fairness Trade-off on Asymmetric Multicore Systems
title_sort Exploring the Throughput-Fairness Trade-off on Asymmetric Multicore Systems
dc.creator.none.fl_str_mv Saez, Juan Carlos
Pousa, Adrián
Castro, Fernando
Chaver, Daniel
Prieto-Matias, Manuel
author Saez, Juan Carlos
author_facet Saez, Juan Carlos
Pousa, Adrián
Castro, Fernando
Chaver, Daniel
Prieto-Matias, Manuel
author_role author
author2 Pousa, Adrián
Castro, Fernando
Chaver, Daniel
Prieto-Matias, Manuel
author2_role author
author
author
author
dc.subject.none.fl_str_mv Informática
asymmetric multicore
Scheduling
Operating systems
topic Informática
asymmetric multicore
Scheduling
Operating systems
dc.description.none.fl_txt_mv Symmetric-ISA (instruction set architecture) asymmetric-performance multicore processors (AMPs) were shown to deliver higher performance per watt and area than symmetric CMPs (Chip Multi-Processors). Previous work has shown that this potential of AMP systems can be realizable thanks to the OS scheduler. Existing scheduling schemes that deliver fairness and priority enforcement on AMPs do not cater to the fact that applications in a multiprogram workload may derive different benefit from using fast cores in the system. As a result, they are likely to perform thread-to-core mappings that degrade the system throughput. To address this limitation, we propose Prop-SP, a scheduling algorithm that aims to improve the throughput-fairness trade-off on AMPs. Our evaluation on real hardware, and using scheduler implementations on a general-purpose OS, reveals that Prop-SP delivers a better throughput-fairness trade-off than state-of-the-art schedulers for a wide variety of multi-application workloads.
Publicado en <i>Lecture Notes in Computer Science</i> book series (LNCS, volume 8806)
Instituto de Investigación en Informática
description Symmetric-ISA (instruction set architecture) asymmetric-performance multicore processors (AMPs) were shown to deliver higher performance per watt and area than symmetric CMPs (Chip Multi-Processors). Previous work has shown that this potential of AMP systems can be realizable thanks to the OS scheduler. Existing scheduling schemes that deliver fairness and priority enforcement on AMPs do not cater to the fact that applications in a multiprogram workload may derive different benefit from using fast cores in the system. As a result, they are likely to perform thread-to-core mappings that degrade the system throughput. To address this limitation, we propose Prop-SP, a scheduling algorithm that aims to improve the throughput-fairness trade-off on AMPs. Our evaluation on real hardware, and using scheduler implementations on a general-purpose OS, reveals that Prop-SP delivers a better throughput-fairness trade-off than state-of-the-art schedulers for a wide variety of multi-application workloads.
publishDate 2014
dc.date.none.fl_str_mv 2014
dc.type.none.fl_str_mv info:eu-repo/semantics/conferenceObject
info:eu-repo/semantics/publishedVersion
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http://purl.org/coar/resource_type/c_5794
info:ar-repo/semantics/documentoDeConferencia
format conferenceObject
status_str publishedVersion
dc.identifier.none.fl_str_mv http://sedici.unlp.edu.ar/handle/10915/132853
url http://sedici.unlp.edu.ar/handle/10915/132853
dc.language.none.fl_str_mv spa
language spa
dc.relation.none.fl_str_mv info:eu-repo/semantics/altIdentifier/isbn/978-3-319-14312-5 978-3-319-14313-2
info:eu-repo/semantics/altIdentifier/issn/0302-9743
info:eu-repo/semantics/altIdentifier/issn/1611-3349
info:eu-repo/semantics/altIdentifier/doi/10.1007/978-3-319-14313-2_28
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by/4.0/
Creative Commons Attribution 4.0 International (CC BY 4.0)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by/4.0/
Creative Commons Attribution 4.0 International (CC BY 4.0)
dc.format.none.fl_str_mv application/pdf
326-337
dc.source.none.fl_str_mv reponame:SEDICI (UNLP)
instname:Universidad Nacional de La Plata
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reponame_str SEDICI (UNLP)
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instname_str Universidad Nacional de La Plata
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repository.name.fl_str_mv SEDICI (UNLP) - Universidad Nacional de La Plata
repository.mail.fl_str_mv alira@sedici.unlp.edu.ar
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