Optimization of throughput, fairness and energy efficiency on asymmetric multicore systems via OS scheduling

Autores
Pousa, Adrián
Año de publicación
2018
Idioma
inglés
Tipo de recurso
reseña artículo
Estado
versión publicada
Descripción
Most of chip multiprocessors (CMPs) are symmetric, i.e. they are composed of identical cores. These CMPs may consist of complex cores (e.g., Intel Haswell or IBM Power8) or simple and lower-power cores (e.g. ARM Cortex A9 or Intel Xeon Phi). Cores in the former approach have advanced microarchitectural features, such as out-of-order super-scalar pipelines, and they are suitable for running sequential applications which use them efficiently. Cores in the latter approach have a simple microarchitecture and are good for running applications with high thread-level parallelism (TLP).
Facultad de Informática
Materia
Ciencias Informáticas
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by/4.0/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/72384
Acceder
id SEDICI_9aad96ac020c16a7e89b8fbaabf5afce
oai_identifier_str oai:sedici.unlp.edu.ar:10915/72384
network_acronym_str SEDICI
repository_id_str 1329
network_name_str SEDICI (UNLP)
spelling Optimization of throughput, fairness and energy efficiency on asymmetric multicore systems via OS schedulingPousa, AdriánCiencias InformáticasMost of chip multiprocessors (CMPs) are symmetric, i.e. they are composed of identical cores. These CMPs may consist of complex cores (e.g., Intel Haswell or IBM Power8) or simple and lower-power cores (e.g. ARM Cortex A9 or Intel Xeon Phi). Cores in the former approach have advanced microarchitectural features, such as out-of-order super-scalar pipelines, and they are suitable for running sequential applications which use them efficiently. Cores in the latter approach have a simple microarchitecture and are good for running applications with high thread-level parallelism (TLP).Facultad de Informática2018-04info:eu-repo/semantics/reviewinfo:eu-repo/semantics/publishedVersionRevisionhttp://purl.org/coar/resource_type/c_dcae04bcinfo:ar-repo/semantics/resenaArticuloapplication/pdf71-72http://sedici.unlp.edu.ar/handle/10915/72384enginfo:eu-repo/semantics/altIdentifier/issn/1666-6038info:eu-repo/semantics/altIdentifier/doi/10.24215/16666038.18.e09info:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by/4.0/Creative Commons Attribution 4.0 International (CC BY 4.0)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-10-15T11:03:54Zoai:sedici.unlp.edu.ar:10915/72384Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-10-15 11:03:55.066SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv Optimization of throughput, fairness and energy efficiency on asymmetric multicore systems via OS scheduling
title Optimization of throughput, fairness and energy efficiency on asymmetric multicore systems via OS scheduling
spellingShingle Optimization of throughput, fairness and energy efficiency on asymmetric multicore systems via OS scheduling
Pousa, Adrián
Ciencias Informáticas
title_short Optimization of throughput, fairness and energy efficiency on asymmetric multicore systems via OS scheduling
title_full Optimization of throughput, fairness and energy efficiency on asymmetric multicore systems via OS scheduling
title_fullStr Optimization of throughput, fairness and energy efficiency on asymmetric multicore systems via OS scheduling
title_full_unstemmed Optimization of throughput, fairness and energy efficiency on asymmetric multicore systems via OS scheduling
title_sort Optimization of throughput, fairness and energy efficiency on asymmetric multicore systems via OS scheduling
dc.creator.none.fl_str_mv Pousa, Adrián
author Pousa, Adrián
author_facet Pousa, Adrián
author_role author
dc.subject.none.fl_str_mv Ciencias Informáticas
topic Ciencias Informáticas
dc.description.none.fl_txt_mv Most of chip multiprocessors (CMPs) are symmetric, i.e. they are composed of identical cores. These CMPs may consist of complex cores (e.g., Intel Haswell or IBM Power8) or simple and lower-power cores (e.g. ARM Cortex A9 or Intel Xeon Phi). Cores in the former approach have advanced microarchitectural features, such as out-of-order super-scalar pipelines, and they are suitable for running sequential applications which use them efficiently. Cores in the latter approach have a simple microarchitecture and are good for running applications with high thread-level parallelism (TLP).
Facultad de Informática
description Most of chip multiprocessors (CMPs) are symmetric, i.e. they are composed of identical cores. These CMPs may consist of complex cores (e.g., Intel Haswell or IBM Power8) or simple and lower-power cores (e.g. ARM Cortex A9 or Intel Xeon Phi). Cores in the former approach have advanced microarchitectural features, such as out-of-order super-scalar pipelines, and they are suitable for running sequential applications which use them efficiently. Cores in the latter approach have a simple microarchitecture and are good for running applications with high thread-level parallelism (TLP).
publishDate 2018
dc.date.none.fl_str_mv 2018-04
dc.type.none.fl_str_mv info:eu-repo/semantics/review
info:eu-repo/semantics/publishedVersion
Revision
http://purl.org/coar/resource_type/c_dcae04bc
info:ar-repo/semantics/resenaArticulo
format review
status_str publishedVersion
dc.identifier.none.fl_str_mv http://sedici.unlp.edu.ar/handle/10915/72384
url http://sedici.unlp.edu.ar/handle/10915/72384
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv info:eu-repo/semantics/altIdentifier/issn/1666-6038
info:eu-repo/semantics/altIdentifier/doi/10.24215/16666038.18.e09
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by/4.0/
Creative Commons Attribution 4.0 International (CC BY 4.0)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by/4.0/
Creative Commons Attribution 4.0 International (CC BY 4.0)
dc.format.none.fl_str_mv application/pdf
71-72
dc.source.none.fl_str_mv reponame:SEDICI (UNLP)
instname:Universidad Nacional de La Plata
instacron:UNLP
reponame_str SEDICI (UNLP)
collection SEDICI (UNLP)
instname_str Universidad Nacional de La Plata
instacron_str UNLP
institution UNLP
repository.name.fl_str_mv SEDICI (UNLP) - Universidad Nacional de La Plata
repository.mail.fl_str_mv alira@sedici.unlp.edu.ar
_version_ 1846064092564946944
score 13.22299

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