A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture

Autores
Chen, Yung-Yuan
Año de publicación
2006
Idioma
inglés
Tipo de recurso
artículo
Estado
versión publicada
Descripción
In this paper, we propose an efficient diagnosis scheme to detect and locate the switching network defects/faults in reconfigurable array architecture. This diagnosis scheme performs the test of switching network based on the scan path and fault intersection test methodology to locate the faults occurring in the switching network. After the diagnosis of switching network, the processing element (PE) test can then be initiated through the good switches and links. Errors in testing that cause a good switch, link or PE to be considered as a bad one is called "killing error". The issue of killing error in testing is addressed and the probability of killing error for our diagnosis technique is analyzed and shown to be extremely low. The significance of this approach is the ability to detect and locate the multiple faults in switches, links, and PEs with low testing circuit overhead, and to offer the good test quality in linear diagnosis time.
Facultad de Informática
Materia
Ciencias Informáticas
Reliability, Testing, and Fault-Tolerance
Arrays
switching network
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by-nc/3.0/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/9511

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spelling A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array ArchitectureChen, Yung-YuanCiencias InformáticasReliability, Testing, and Fault-ToleranceArraysswitching networkIn this paper, we propose an efficient diagnosis scheme to detect and locate the switching network defects/faults in reconfigurable array architecture. This diagnosis scheme performs the test of switching network based on the scan path and fault intersection test methodology to locate the faults occurring in the switching network. After the diagnosis of switching network, the processing element (PE) test can then be initiated through the good switches and links. Errors in testing that cause a good switch, link or PE to be considered as a bad one is called "killing error". The issue of killing error in testing is addressed and the probability of killing error for our diagnosis technique is analyzed and shown to be extremely low. The significance of this approach is the ability to detect and locate the multiple faults in switches, links, and PEs with low testing circuit overhead, and to offer the good test quality in linear diagnosis time.Facultad de Informática2006-04info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionArticulohttp://purl.org/coar/resource_type/c_6501info:ar-repo/semantics/articuloapplication/pdf12-21http://sedici.unlp.edu.ar/handle/10915/9511enginfo:eu-repo/semantics/altIdentifier/url/http://journal.info.unlp.edu.ar/wp-content/uploads/JCST-Apr06-3.pdfinfo:eu-repo/semantics/altIdentifier/issn/1666-6038info:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc/3.0/Creative Commons Attribution-NonCommercial 3.0 Unported (CC BY-NC 3.0)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-03T10:23:34Zoai:sedici.unlp.edu.ar:10915/9511Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-03 10:23:34.582SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture
title A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture
spellingShingle A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture
Chen, Yung-Yuan
Ciencias Informáticas
Reliability, Testing, and Fault-Tolerance
Arrays
switching network
title_short A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture
title_full A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture
title_fullStr A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture
title_full_unstemmed A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture
title_sort A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture
dc.creator.none.fl_str_mv Chen, Yung-Yuan
author Chen, Yung-Yuan
author_facet Chen, Yung-Yuan
author_role author
dc.subject.none.fl_str_mv Ciencias Informáticas
Reliability, Testing, and Fault-Tolerance
Arrays
switching network
topic Ciencias Informáticas
Reliability, Testing, and Fault-Tolerance
Arrays
switching network
dc.description.none.fl_txt_mv In this paper, we propose an efficient diagnosis scheme to detect and locate the switching network defects/faults in reconfigurable array architecture. This diagnosis scheme performs the test of switching network based on the scan path and fault intersection test methodology to locate the faults occurring in the switching network. After the diagnosis of switching network, the processing element (PE) test can then be initiated through the good switches and links. Errors in testing that cause a good switch, link or PE to be considered as a bad one is called "killing error". The issue of killing error in testing is addressed and the probability of killing error for our diagnosis technique is analyzed and shown to be extremely low. The significance of this approach is the ability to detect and locate the multiple faults in switches, links, and PEs with low testing circuit overhead, and to offer the good test quality in linear diagnosis time.
Facultad de Informática
description In this paper, we propose an efficient diagnosis scheme to detect and locate the switching network defects/faults in reconfigurable array architecture. This diagnosis scheme performs the test of switching network based on the scan path and fault intersection test methodology to locate the faults occurring in the switching network. After the diagnosis of switching network, the processing element (PE) test can then be initiated through the good switches and links. Errors in testing that cause a good switch, link or PE to be considered as a bad one is called "killing error". The issue of killing error in testing is addressed and the probability of killing error for our diagnosis technique is analyzed and shown to be extremely low. The significance of this approach is the ability to detect and locate the multiple faults in switches, links, and PEs with low testing circuit overhead, and to offer the good test quality in linear diagnosis time.
publishDate 2006
dc.date.none.fl_str_mv 2006-04
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
Articulo
http://purl.org/coar/resource_type/c_6501
info:ar-repo/semantics/articulo
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv http://sedici.unlp.edu.ar/handle/10915/9511
url http://sedici.unlp.edu.ar/handle/10915/9511
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv info:eu-repo/semantics/altIdentifier/url/http://journal.info.unlp.edu.ar/wp-content/uploads/JCST-Apr06-3.pdf
info:eu-repo/semantics/altIdentifier/issn/1666-6038
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by-nc/3.0/
Creative Commons Attribution-NonCommercial 3.0 Unported (CC BY-NC 3.0)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc/3.0/
Creative Commons Attribution-NonCommercial 3.0 Unported (CC BY-NC 3.0)
dc.format.none.fl_str_mv application/pdf
12-21
dc.source.none.fl_str_mv reponame:SEDICI (UNLP)
instname:Universidad Nacional de La Plata
instacron:UNLP
reponame_str SEDICI (UNLP)
collection SEDICI (UNLP)
instname_str Universidad Nacional de La Plata
instacron_str UNLP
institution UNLP
repository.name.fl_str_mv SEDICI (UNLP) - Universidad Nacional de La Plata
repository.mail.fl_str_mv alira@sedici.unlp.edu.ar
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