Designing a scalable simultaneous multithreaded processor

Autores
Moure, Juan Carlos; Rexachs del Rosario, Dolores; Luque Fadón, Emilio
Año de publicación
2000
Idioma
inglés
Tipo de recurso
documento de conferencia
Estado
versión publicada
Descripción
This paper analyzes the basic design issues of multithreaded processors and discusses how they may reach the performance requirements of current workloads, taking into account current technological trends. We compare the multithreaded proposal with current single-thread altematives like superscalar and EPIC. W e present scalable simultaneous multithreading, a new design approach that balances the exploitation of instruction- and thread-level parallelism, combining static and dynamic mechanisms to maximize overall performance. W e first discuss results from a preliminary study of its suitability and then address a more indepth analysis of the design of one of its parts, the fetch unit. Results from a comprehensive study of the interference of threads on the fetch unit's shared resources are used to propose a detailed fetch unit microarchitecture. Its balanced organization and its reconfiguration capability assure both maximum singlethread performance and optimized multithreaded execution.
I Workshop de Procesamiento Distribuido y Paralelo (WPDP)
Red de Universidades con Carreras en Informática (RedUNCI)
Materia
Ciencias Informáticas
simultaneous multithreaded processors
fetch unit
Parallel Architectures
Threads
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/23357
Acceder
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oai_identifier_str oai:sedici.unlp.edu.ar:10915/23357
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repository_id_str 1329
network_name_str SEDICI (UNLP)
spelling Designing a scalable simultaneous multithreaded processorMoure, Juan CarlosRexachs del Rosario, DoloresLuque Fadón, EmilioCiencias Informáticassimultaneous multithreaded processorsfetch unitParallel ArchitecturesThreadsThis paper analyzes the basic design issues of multithreaded processors and discusses how they may reach the performance requirements of current workloads, taking into account current technological trends. We compare the multithreaded proposal with current single-thread altematives like superscalar and EPIC. W e present scalable simultaneous multithreading, a new design approach that balances the exploitation of instruction- and thread-level parallelism, combining static and dynamic mechanisms to maximize overall performance. W e first discuss results from a preliminary study of its suitability and then address a more indepth analysis of the design of one of its parts, the fetch unit. Results from a comprehensive study of the interference of threads on the fetch unit's shared resources are used to propose a detailed fetch unit microarchitecture. Its balanced organization and its reconfiguration capability assure both maximum singlethread performance and optimized multithreaded execution.I Workshop de Procesamiento Distribuido y Paralelo (WPDP)Red de Universidades con Carreras en Informática (RedUNCI)2000-10info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdfhttp://sedici.unlp.edu.ar/handle/10915/23357enginfo:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-sa/2.5/ar/Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-12-23T10:58:16Zoai:sedici.unlp.edu.ar:10915/23357Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-12-23 10:58:16.589SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv Designing a scalable simultaneous multithreaded processor
title Designing a scalable simultaneous multithreaded processor
spellingShingle Designing a scalable simultaneous multithreaded processor
Moure, Juan Carlos
Ciencias Informáticas
simultaneous multithreaded processors
fetch unit
Parallel Architectures
Threads
title_short Designing a scalable simultaneous multithreaded processor
title_full Designing a scalable simultaneous multithreaded processor
title_fullStr Designing a scalable simultaneous multithreaded processor
title_full_unstemmed Designing a scalable simultaneous multithreaded processor
title_sort Designing a scalable simultaneous multithreaded processor
dc.creator.none.fl_str_mv Moure, Juan Carlos
Rexachs del Rosario, Dolores
Luque Fadón, Emilio
author Moure, Juan Carlos
author_facet Moure, Juan Carlos
Rexachs del Rosario, Dolores
Luque Fadón, Emilio
author_role author
author2 Rexachs del Rosario, Dolores
Luque Fadón, Emilio
author2_role author
author
dc.subject.none.fl_str_mv Ciencias Informáticas
simultaneous multithreaded processors
fetch unit
Parallel Architectures
Threads
topic Ciencias Informáticas
simultaneous multithreaded processors
fetch unit
Parallel Architectures
Threads
dc.description.none.fl_txt_mv This paper analyzes the basic design issues of multithreaded processors and discusses how they may reach the performance requirements of current workloads, taking into account current technological trends. We compare the multithreaded proposal with current single-thread altematives like superscalar and EPIC. W e present scalable simultaneous multithreading, a new design approach that balances the exploitation of instruction- and thread-level parallelism, combining static and dynamic mechanisms to maximize overall performance. W e first discuss results from a preliminary study of its suitability and then address a more indepth analysis of the design of one of its parts, the fetch unit. Results from a comprehensive study of the interference of threads on the fetch unit's shared resources are used to propose a detailed fetch unit microarchitecture. Its balanced organization and its reconfiguration capability assure both maximum singlethread performance and optimized multithreaded execution.
I Workshop de Procesamiento Distribuido y Paralelo (WPDP)
Red de Universidades con Carreras en Informática (RedUNCI)
description This paper analyzes the basic design issues of multithreaded processors and discusses how they may reach the performance requirements of current workloads, taking into account current technological trends. We compare the multithreaded proposal with current single-thread altematives like superscalar and EPIC. W e present scalable simultaneous multithreading, a new design approach that balances the exploitation of instruction- and thread-level parallelism, combining static and dynamic mechanisms to maximize overall performance. W e first discuss results from a preliminary study of its suitability and then address a more indepth analysis of the design of one of its parts, the fetch unit. Results from a comprehensive study of the interference of threads on the fetch unit's shared resources are used to propose a detailed fetch unit microarchitecture. Its balanced organization and its reconfiguration capability assure both maximum singlethread performance and optimized multithreaded execution.
publishDate 2000
dc.date.none.fl_str_mv 2000-10
dc.type.none.fl_str_mv info:eu-repo/semantics/conferenceObject
info:eu-repo/semantics/publishedVersion
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status_str publishedVersion
dc.identifier.none.fl_str_mv http://sedici.unlp.edu.ar/handle/10915/23357
url http://sedici.unlp.edu.ar/handle/10915/23357
dc.language.none.fl_str_mv eng
language eng
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
dc.format.none.fl_str_mv application/pdf
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reponame_str SEDICI (UNLP)
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instname_str Universidad Nacional de La Plata
instacron_str UNLP
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repository.name.fl_str_mv SEDICI (UNLP) - Universidad Nacional de La Plata
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