A Low Complexity Sum-Subtract Decoding Algorithm for Non-Binary LDPC Codes over GF(q)

Autores
Arnone, Leonardo; Castiñeira Moreira, Jorge; Gayoso, Carlos; González, Claudio; Rabini, Miguel
Año de publicación
2010
Idioma
inglés
Tipo de recurso
documento de conferencia
Estado
versión publicada
Descripción
In this paper, we present a low complexity Sum-Subtract decoder for non-binary LDPC codes defined over GF(q). The performance of this decoding algorithm is similar to that of the Fast Fourier Transform Sum-Product algorithm usually utilized for decoding non-binary LDPC codes. It is a simplified algorithm that can be easily implemented on programmable logic technology such as FPGA devices because of its use of only additions and subtractions, avoiding the use of quotients and products, and of float point arithmetic. The algorithm yields a very low complexity programmable logic implementation of an NB-LDPC decoder with an excellent BER performance.
Sociedad Argentina de Informática e Investigación Operativa
Materia
Ciencias Informáticas
Galois fields
non-binary LDPC codes
programmable logic technology
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by-nc-sa/4.0/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/152747
Acceder
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oai_identifier_str oai:sedici.unlp.edu.ar:10915/152747
network_acronym_str SEDICI
repository_id_str 1329
network_name_str SEDICI (UNLP)
spelling A Low Complexity Sum-Subtract Decoding Algorithm for Non-Binary LDPC Codes over GF(q)Arnone, LeonardoCastiñeira Moreira, JorgeGayoso, CarlosGonzález, ClaudioRabini, MiguelCiencias InformáticasGalois fieldsnon-binary LDPC codesprogrammable logic technologyIn this paper, we present a low complexity Sum-Subtract decoder for non-binary LDPC codes defined over GF(q). The performance of this decoding algorithm is similar to that of the Fast Fourier Transform Sum-Product algorithm usually utilized for decoding non-binary LDPC codes. It is a simplified algorithm that can be easily implemented on programmable logic technology such as FPGA devices because of its use of only additions and subtractions, avoiding the use of quotients and products, and of float point arithmetic. The algorithm yields a very low complexity programmable logic implementation of an NB-LDPC decoder with an excellent BER performance.Sociedad Argentina de Informática e Investigación Operativa2010info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdf1751-1758http://sedici.unlp.edu.ar/handle/10915/152747enginfo:eu-repo/semantics/altIdentifier/url/http://39jaiio.sadio.org.ar/sites/default/files/39-jaiio-ast-22.pdfinfo:eu-repo/semantics/altIdentifier/issn/1850-2806info:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-sa/4.0/Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-03T11:11:24Zoai:sedici.unlp.edu.ar:10915/152747Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-03 11:11:24.533SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv A Low Complexity Sum-Subtract Decoding Algorithm for Non-Binary LDPC Codes over GF(q)
title A Low Complexity Sum-Subtract Decoding Algorithm for Non-Binary LDPC Codes over GF(q)
spellingShingle A Low Complexity Sum-Subtract Decoding Algorithm for Non-Binary LDPC Codes over GF(q)
Arnone, Leonardo
Ciencias Informáticas
Galois fields
non-binary LDPC codes
programmable logic technology
title_short A Low Complexity Sum-Subtract Decoding Algorithm for Non-Binary LDPC Codes over GF(q)
title_full A Low Complexity Sum-Subtract Decoding Algorithm for Non-Binary LDPC Codes over GF(q)
title_fullStr A Low Complexity Sum-Subtract Decoding Algorithm for Non-Binary LDPC Codes over GF(q)
title_full_unstemmed A Low Complexity Sum-Subtract Decoding Algorithm for Non-Binary LDPC Codes over GF(q)
title_sort A Low Complexity Sum-Subtract Decoding Algorithm for Non-Binary LDPC Codes over GF(q)
dc.creator.none.fl_str_mv Arnone, Leonardo
Castiñeira Moreira, Jorge
Gayoso, Carlos
González, Claudio
Rabini, Miguel
author Arnone, Leonardo
author_facet Arnone, Leonardo
Castiñeira Moreira, Jorge
Gayoso, Carlos
González, Claudio
Rabini, Miguel
author_role author
author2 Castiñeira Moreira, Jorge
Gayoso, Carlos
González, Claudio
Rabini, Miguel
author2_role author
author
author
author
dc.subject.none.fl_str_mv Ciencias Informáticas
Galois fields
non-binary LDPC codes
programmable logic technology
topic Ciencias Informáticas
Galois fields
non-binary LDPC codes
programmable logic technology
dc.description.none.fl_txt_mv In this paper, we present a low complexity Sum-Subtract decoder for non-binary LDPC codes defined over GF(q). The performance of this decoding algorithm is similar to that of the Fast Fourier Transform Sum-Product algorithm usually utilized for decoding non-binary LDPC codes. It is a simplified algorithm that can be easily implemented on programmable logic technology such as FPGA devices because of its use of only additions and subtractions, avoiding the use of quotients and products, and of float point arithmetic. The algorithm yields a very low complexity programmable logic implementation of an NB-LDPC decoder with an excellent BER performance.
Sociedad Argentina de Informática e Investigación Operativa
description In this paper, we present a low complexity Sum-Subtract decoder for non-binary LDPC codes defined over GF(q). The performance of this decoding algorithm is similar to that of the Fast Fourier Transform Sum-Product algorithm usually utilized for decoding non-binary LDPC codes. It is a simplified algorithm that can be easily implemented on programmable logic technology such as FPGA devices because of its use of only additions and subtractions, avoiding the use of quotients and products, and of float point arithmetic. The algorithm yields a very low complexity programmable logic implementation of an NB-LDPC decoder with an excellent BER performance.
publishDate 2010
dc.date.none.fl_str_mv 2010
dc.type.none.fl_str_mv info:eu-repo/semantics/conferenceObject
info:eu-repo/semantics/publishedVersion
Objeto de conferencia
http://purl.org/coar/resource_type/c_5794
info:ar-repo/semantics/documentoDeConferencia
format conferenceObject
status_str publishedVersion
dc.identifier.none.fl_str_mv http://sedici.unlp.edu.ar/handle/10915/152747
url http://sedici.unlp.edu.ar/handle/10915/152747
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv info:eu-repo/semantics/altIdentifier/url/http://39jaiio.sadio.org.ar/sites/default/files/39-jaiio-ast-22.pdf
info:eu-repo/semantics/altIdentifier/issn/1850-2806
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by-nc-sa/4.0/
Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc-sa/4.0/
Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)
dc.format.none.fl_str_mv application/pdf
1751-1758
dc.source.none.fl_str_mv reponame:SEDICI (UNLP)
instname:Universidad Nacional de La Plata
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reponame_str SEDICI (UNLP)
collection SEDICI (UNLP)
instname_str Universidad Nacional de La Plata
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institution UNLP
repository.name.fl_str_mv SEDICI (UNLP) - Universidad Nacional de La Plata
repository.mail.fl_str_mv alira@sedici.unlp.edu.ar
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