Field programmable gate arrays implementations of low complexity soft-input soft-output low-density parity-check decoders

Autores
Arnone, Leonardo Jose; Castiñeira Moreira, Jorge; Farrell, P. G.
Año de publicación
2012
Idioma
inglés
Tipo de recurso
artículo
Estado
versión publicada
Descripción
Low-density parity-check (LDPC) codes are very efficient error control codes that are being considered for use in many next-generation communication systems. In this study low complexity soft-input, soft-output (SISO) field programmable gate arrays (FPGA) implementations of a novel logarithmic sum-product (LogSP) iterative LDPC decoder and a recently proposed simplified soft Euclidean distance (SSD) iterative LDPC decoder are presented, and their complexities and performance are compared. These implementations operate over any choice of parity check matrix (including those randomly generated, structurally generated and either systematic or non-systematic) and can be parametrically adapted for any code rate. The proposed implementations are both of very low complexity, because they operate using only sums, subtractions, comparisons and look-up tables, which makes them particularly suitable for FPGA realisation. The SSD decoder has a lower implementation complexity than the LogSP LDPC decoder and it also offers the advantage of not requiring knowledge of the channel signal-to-noise ratio, unlike most other LDPC decoders.
Fil: Arnone, Leonardo Jose. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Departamento de Ingeniería Eléctrica; Argentina
Fil: Castiñeira Moreira, Jorge. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Departamento de Ingeniería Eléctrica; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Mar del Plata; Argentina
Fil: Farrell, P. G.. Lancaster University; Reino Unido
Materia
FPGA IMPLEMENTATION
EUCLIDEAN METRIC
LDPC CODES
Nivel de accesibilidad
acceso abierto
Condiciones de uso
https://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Repositorio
CONICET Digital (CONICET)
Institución
Consejo Nacional de Investigaciones Científicas y Técnicas
OAI Identificador
oai:ri.conicet.gov.ar:11336/212607
Acceder
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oai_identifier_str oai:ri.conicet.gov.ar:11336/212607
network_acronym_str CONICETDig
repository_id_str 3498
network_name_str CONICET Digital (CONICET)
spelling Field programmable gate arrays implementations of low complexity soft-input soft-output low-density parity-check decodersArnone, Leonardo JoseCastiñeira Moreira, JorgeFarrell, P. G.FPGA IMPLEMENTATIONEUCLIDEAN METRICLDPC CODEShttps://purl.org/becyt/ford/2.2https://purl.org/becyt/ford/2Low-density parity-check (LDPC) codes are very efficient error control codes that are being considered for use in many next-generation communication systems. In this study low complexity soft-input, soft-output (SISO) field programmable gate arrays (FPGA) implementations of a novel logarithmic sum-product (LogSP) iterative LDPC decoder and a recently proposed simplified soft Euclidean distance (SSD) iterative LDPC decoder are presented, and their complexities and performance are compared. These implementations operate over any choice of parity check matrix (including those randomly generated, structurally generated and either systematic or non-systematic) and can be parametrically adapted for any code rate. The proposed implementations are both of very low complexity, because they operate using only sums, subtractions, comparisons and look-up tables, which makes them particularly suitable for FPGA realisation. The SSD decoder has a lower implementation complexity than the LogSP LDPC decoder and it also offers the advantage of not requiring knowledge of the channel signal-to-noise ratio, unlike most other LDPC decoders.Fil: Arnone, Leonardo Jose. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Departamento de Ingeniería Eléctrica; ArgentinaFil: Castiñeira Moreira, Jorge. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Departamento de Ingeniería Eléctrica; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Mar del Plata; ArgentinaFil: Farrell, P. G.. Lancaster University; Reino UnidoInstitution of Engineering and Technology2012-08info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionhttp://purl.org/coar/resource_type/c_6501info:ar-repo/semantics/articuloapplication/pdfapplication/pdfhttp://hdl.handle.net/11336/212607Arnone, Leonardo Jose; Castiñeira Moreira, Jorge; Farrell, P. G.; Field programmable gate arrays implementations of low complexity soft-input soft-output low-density parity-check decoders; Institution of Engineering and Technology; Iet Communications; 6; 12; 8-2012; 1670-16751751-8628CONICET DigitalCONICETenginfo:eu-repo/semantics/altIdentifier/url/https://digital-library.theiet.org/content/journals/10.1049/iet-com.2011.0767info:eu-repo/semantics/altIdentifier/doi/10.1049/iet-com.2011.0767info:eu-repo/semantics/openAccesshttps://creativecommons.org/licenses/by-nc-sa/2.5/ar/reponame:CONICET Digital (CONICET)instname:Consejo Nacional de Investigaciones Científicas y Técnicas2025-09-03T09:47:28Zoai:ri.conicet.gov.ar:11336/212607instacron:CONICETInstitucionalhttp://ri.conicet.gov.ar/Organismo científico-tecnológicoNo correspondehttp://ri.conicet.gov.ar/oai/requestdasensio@conicet.gov.ar; lcarlino@conicet.gov.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:34982025-09-03 09:47:29.219CONICET Digital (CONICET) - Consejo Nacional de Investigaciones Científicas y Técnicasfalse
dc.title.none.fl_str_mv Field programmable gate arrays implementations of low complexity soft-input soft-output low-density parity-check decoders
title Field programmable gate arrays implementations of low complexity soft-input soft-output low-density parity-check decoders
spellingShingle Field programmable gate arrays implementations of low complexity soft-input soft-output low-density parity-check decoders
Arnone, Leonardo Jose
FPGA IMPLEMENTATION
EUCLIDEAN METRIC
LDPC CODES
title_short Field programmable gate arrays implementations of low complexity soft-input soft-output low-density parity-check decoders
title_full Field programmable gate arrays implementations of low complexity soft-input soft-output low-density parity-check decoders
title_fullStr Field programmable gate arrays implementations of low complexity soft-input soft-output low-density parity-check decoders
title_full_unstemmed Field programmable gate arrays implementations of low complexity soft-input soft-output low-density parity-check decoders
title_sort Field programmable gate arrays implementations of low complexity soft-input soft-output low-density parity-check decoders
dc.creator.none.fl_str_mv Arnone, Leonardo Jose
Castiñeira Moreira, Jorge
Farrell, P. G.
author Arnone, Leonardo Jose
author_facet Arnone, Leonardo Jose
Castiñeira Moreira, Jorge
Farrell, P. G.
author_role author
author2 Castiñeira Moreira, Jorge
Farrell, P. G.
author2_role author
author
dc.subject.none.fl_str_mv FPGA IMPLEMENTATION
EUCLIDEAN METRIC
LDPC CODES
topic FPGA IMPLEMENTATION
EUCLIDEAN METRIC
LDPC CODES
purl_subject.fl_str_mv https://purl.org/becyt/ford/2.2
https://purl.org/becyt/ford/2
dc.description.none.fl_txt_mv Low-density parity-check (LDPC) codes are very efficient error control codes that are being considered for use in many next-generation communication systems. In this study low complexity soft-input, soft-output (SISO) field programmable gate arrays (FPGA) implementations of a novel logarithmic sum-product (LogSP) iterative LDPC decoder and a recently proposed simplified soft Euclidean distance (SSD) iterative LDPC decoder are presented, and their complexities and performance are compared. These implementations operate over any choice of parity check matrix (including those randomly generated, structurally generated and either systematic or non-systematic) and can be parametrically adapted for any code rate. The proposed implementations are both of very low complexity, because they operate using only sums, subtractions, comparisons and look-up tables, which makes them particularly suitable for FPGA realisation. The SSD decoder has a lower implementation complexity than the LogSP LDPC decoder and it also offers the advantage of not requiring knowledge of the channel signal-to-noise ratio, unlike most other LDPC decoders.
Fil: Arnone, Leonardo Jose. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Departamento de Ingeniería Eléctrica; Argentina
Fil: Castiñeira Moreira, Jorge. Universidad Nacional de Mar del Plata. Facultad de Ingeniería. Departamento de Ingeniería Eléctrica; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Mar del Plata; Argentina
Fil: Farrell, P. G.. Lancaster University; Reino Unido
description Low-density parity-check (LDPC) codes are very efficient error control codes that are being considered for use in many next-generation communication systems. In this study low complexity soft-input, soft-output (SISO) field programmable gate arrays (FPGA) implementations of a novel logarithmic sum-product (LogSP) iterative LDPC decoder and a recently proposed simplified soft Euclidean distance (SSD) iterative LDPC decoder are presented, and their complexities and performance are compared. These implementations operate over any choice of parity check matrix (including those randomly generated, structurally generated and either systematic or non-systematic) and can be parametrically adapted for any code rate. The proposed implementations are both of very low complexity, because they operate using only sums, subtractions, comparisons and look-up tables, which makes them particularly suitable for FPGA realisation. The SSD decoder has a lower implementation complexity than the LogSP LDPC decoder and it also offers the advantage of not requiring knowledge of the channel signal-to-noise ratio, unlike most other LDPC decoders.
publishDate 2012
dc.date.none.fl_str_mv 2012-08
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
http://purl.org/coar/resource_type/c_6501
info:ar-repo/semantics/articulo
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv http://hdl.handle.net/11336/212607
Arnone, Leonardo Jose; Castiñeira Moreira, Jorge; Farrell, P. G.; Field programmable gate arrays implementations of low complexity soft-input soft-output low-density parity-check decoders; Institution of Engineering and Technology; Iet Communications; 6; 12; 8-2012; 1670-1675
1751-8628
CONICET Digital
CONICET
url http://hdl.handle.net/11336/212607
identifier_str_mv Arnone, Leonardo Jose; Castiñeira Moreira, Jorge; Farrell, P. G.; Field programmable gate arrays implementations of low complexity soft-input soft-output low-density parity-check decoders; Institution of Engineering and Technology; Iet Communications; 6; 12; 8-2012; 1670-1675
1751-8628
CONICET Digital
CONICET
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv info:eu-repo/semantics/altIdentifier/url/https://digital-library.theiet.org/content/journals/10.1049/iet-com.2011.0767
info:eu-repo/semantics/altIdentifier/doi/10.1049/iet-com.2011.0767
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
https://creativecommons.org/licenses/by-nc-sa/2.5/ar/
eu_rights_str_mv openAccess
rights_invalid_str_mv https://creativecommons.org/licenses/by-nc-sa/2.5/ar/
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv Institution of Engineering and Technology
publisher.none.fl_str_mv Institution of Engineering and Technology
dc.source.none.fl_str_mv reponame:CONICET Digital (CONICET)
instname:Consejo Nacional de Investigaciones Científicas y Técnicas
reponame_str CONICET Digital (CONICET)
collection CONICET Digital (CONICET)
instname_str Consejo Nacional de Investigaciones Científicas y Técnicas
repository.name.fl_str_mv CONICET Digital (CONICET) - Consejo Nacional de Investigaciones Científicas y Técnicas
repository.mail.fl_str_mv dasensio@conicet.gov.ar; lcarlino@conicet.gov.ar
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score 13.13397

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