Comparison of Synchrophasor Estimation Methods in Simulation Environment and Real Hardware Implementation

Autores
Leibovich, Pablo Ezequiel; Issouribehere, Fernando; Barbero, Juan Carlos
Año de publicación
2018
Idioma
inglés
Tipo de recurso
documento de conferencia
Estado
versión publicada
Descripción
This paper presents a description and performance comparison of two synchrophasor estimation algorithms proposed in the literature. The theoretical error performance is analyzed and compared with a practical implementation. Both synchrophasor estimators were implemented in a low cost hardware architecture proposed in the paper, with the purpose of showing the inherent estimator errors and the external error factors such as noise, quantization errors and sampling clock affected by jitter. In order to test the estimation algorithms, analysis under steady-state and dynamic conditions were performed. The tests were made under the conditions specified in the IEEE Standard C37.118.1-2011 and the total vector error of the algorithms was considered as the performance index. The studied and implemented algorithms were chosen by its nature, so one is based on frequency-domain analysis making an Interpolated-Discrete Fourier Transform and the other is based on time-domain analysis, implementing frequency mixing and a low pass FIR filter.
Instituto de Investigaciones Tecnológicas para Redes y Equipos Eléctricos
Materia
Ingeniería
Error analysis
Microcontroller
Phasor measurement unit
Signal processing
Synchrophasor
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by-nc-nd/4.0/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/90518
Acceder
id SEDICI_21d21b2381c4767290a3343abce295ea
oai_identifier_str oai:sedici.unlp.edu.ar:10915/90518
network_acronym_str SEDICI
repository_id_str 1329
network_name_str SEDICI (UNLP)
spelling Comparison of Synchrophasor Estimation Methods in Simulation Environment and Real Hardware ImplementationLeibovich, Pablo EzequielIssouribehere, FernandoBarbero, Juan CarlosIngenieríaError analysisMicrocontrollerPhasor measurement unitSignal processingSynchrophasorThis paper presents a description and performance comparison of two synchrophasor estimation algorithms proposed in the literature. The theoretical error performance is analyzed and compared with a practical implementation. Both synchrophasor estimators were implemented in a low cost hardware architecture proposed in the paper, with the purpose of showing the inherent estimator errors and the external error factors such as noise, quantization errors and sampling clock affected by jitter. In order to test the estimation algorithms, analysis under steady-state and dynamic conditions were performed. The tests were made under the conditions specified in the IEEE Standard C37.118.1-2011 and the total vector error of the algorithms was considered as the performance index. The studied and implemented algorithms were chosen by its nature, so one is based on frequency-domain analysis making an Interpolated-Discrete Fourier Transform and the other is based on time-domain analysis, implementing frequency mixing and a low pass FIR filter.Instituto de Investigaciones Tecnológicas para Redes y Equipos Eléctricos2018-08-05info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdfhttp://sedici.unlp.edu.ar/handle/10915/90518enginfo:eu-repo/semantics/altIdentifier/isbn/978-1-5386-7703-2info:eu-repo/semantics/altIdentifier/url/https://app.box.com/s/eddkuuzit9b8gumjqsprdqa1zqopyrccinfo:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-nd/4.0/Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-10-15T11:10:31Zoai:sedici.unlp.edu.ar:10915/90518Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-10-15 11:10:32.164SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv Comparison of Synchrophasor Estimation Methods in Simulation Environment and Real Hardware Implementation
title Comparison of Synchrophasor Estimation Methods in Simulation Environment and Real Hardware Implementation
spellingShingle Comparison of Synchrophasor Estimation Methods in Simulation Environment and Real Hardware Implementation
Leibovich, Pablo Ezequiel
Ingeniería
Error analysis
Microcontroller
Phasor measurement unit
Signal processing
Synchrophasor
title_short Comparison of Synchrophasor Estimation Methods in Simulation Environment and Real Hardware Implementation
title_full Comparison of Synchrophasor Estimation Methods in Simulation Environment and Real Hardware Implementation
title_fullStr Comparison of Synchrophasor Estimation Methods in Simulation Environment and Real Hardware Implementation
title_full_unstemmed Comparison of Synchrophasor Estimation Methods in Simulation Environment and Real Hardware Implementation
title_sort Comparison of Synchrophasor Estimation Methods in Simulation Environment and Real Hardware Implementation
dc.creator.none.fl_str_mv Leibovich, Pablo Ezequiel
Issouribehere, Fernando
Barbero, Juan Carlos
author Leibovich, Pablo Ezequiel
author_facet Leibovich, Pablo Ezequiel
Issouribehere, Fernando
Barbero, Juan Carlos
author_role author
author2 Issouribehere, Fernando
Barbero, Juan Carlos
author2_role author
author
dc.subject.none.fl_str_mv Ingeniería
Error analysis
Microcontroller
Phasor measurement unit
Signal processing
Synchrophasor
topic Ingeniería
Error analysis
Microcontroller
Phasor measurement unit
Signal processing
Synchrophasor
dc.description.none.fl_txt_mv This paper presents a description and performance comparison of two synchrophasor estimation algorithms proposed in the literature. The theoretical error performance is analyzed and compared with a practical implementation. Both synchrophasor estimators were implemented in a low cost hardware architecture proposed in the paper, with the purpose of showing the inherent estimator errors and the external error factors such as noise, quantization errors and sampling clock affected by jitter. In order to test the estimation algorithms, analysis under steady-state and dynamic conditions were performed. The tests were made under the conditions specified in the IEEE Standard C37.118.1-2011 and the total vector error of the algorithms was considered as the performance index. The studied and implemented algorithms were chosen by its nature, so one is based on frequency-domain analysis making an Interpolated-Discrete Fourier Transform and the other is based on time-domain analysis, implementing frequency mixing and a low pass FIR filter.
Instituto de Investigaciones Tecnológicas para Redes y Equipos Eléctricos
description This paper presents a description and performance comparison of two synchrophasor estimation algorithms proposed in the literature. The theoretical error performance is analyzed and compared with a practical implementation. Both synchrophasor estimators were implemented in a low cost hardware architecture proposed in the paper, with the purpose of showing the inherent estimator errors and the external error factors such as noise, quantization errors and sampling clock affected by jitter. In order to test the estimation algorithms, analysis under steady-state and dynamic conditions were performed. The tests were made under the conditions specified in the IEEE Standard C37.118.1-2011 and the total vector error of the algorithms was considered as the performance index. The studied and implemented algorithms were chosen by its nature, so one is based on frequency-domain analysis making an Interpolated-Discrete Fourier Transform and the other is based on time-domain analysis, implementing frequency mixing and a low pass FIR filter.
publishDate 2018
dc.date.none.fl_str_mv 2018-08-05
dc.type.none.fl_str_mv info:eu-repo/semantics/conferenceObject
info:eu-repo/semantics/publishedVersion
Objeto de conferencia
http://purl.org/coar/resource_type/c_5794
info:ar-repo/semantics/documentoDeConferencia
format conferenceObject
status_str publishedVersion
dc.identifier.none.fl_str_mv http://sedici.unlp.edu.ar/handle/10915/90518
url http://sedici.unlp.edu.ar/handle/10915/90518
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv info:eu-repo/semantics/altIdentifier/isbn/978-1-5386-7703-2
info:eu-repo/semantics/altIdentifier/url/https://app.box.com/s/eddkuuzit9b8gumjqsprdqa1zqopyrcc
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by-nc-nd/4.0/
Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc-nd/4.0/
Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0)
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:SEDICI (UNLP)
instname:Universidad Nacional de La Plata
instacron:UNLP
reponame_str SEDICI (UNLP)
collection SEDICI (UNLP)
instname_str Universidad Nacional de La Plata
instacron_str UNLP
institution UNLP
repository.name.fl_str_mv SEDICI (UNLP) - Universidad Nacional de La Plata
repository.mail.fl_str_mv alira@sedici.unlp.edu.ar
_version_ 1846064162247016448
score 13.22299

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