Speckle signal processing through FPGA
- Autores
- Todorovich, Elías; Vázquez, Martín; Cozzolino, Ezequiel; Ferrara, Fernando; Bioul, Géry Jean Antoine; Dai Para, A. L.; Passoni, Lucía Isabel
- Año de publicación
- 2011
- Idioma
- inglés
- Tipo de recurso
- documento de conferencia
- Estado
- versión publicada
- Descripción
- This paper introduces Field Programmable Gate Array (FPGA) technology as an alternative platform to implement algorithms for speckle patterns analysis in real time. Functions and algorithmic procedures have been expressed in pseudo languages then in Hardware Description Languages (HDL). For all cases, time performances are presented for the Xilinx Virtex-6 family. Comparisons are also made with PC platform implementations presented in the literature.
Sección: Diseño de hardware FPGA
Centro de Técnicas Analógico-Digitales - Materia
-
Ingeniería
Speckle patterns
Granular computing
Real time synthesis
FPGA - Nivel de accesibilidad
- acceso abierto
- Condiciones de uso
- http://creativecommons.org/licenses/by-nc-sa/4.0/
- Repositorio
- Institución
- Universidad Nacional de La Plata
- OAI Identificador
- oai:sedici.unlp.edu.ar:10915/121411
Ver los metadatos del registro completo
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Speckle signal processing through FPGATodorovich, ElíasVázquez, MartínCozzolino, EzequielFerrara, FernandoBioul, Géry Jean AntoineDai Para, A. L.Passoni, Lucía IsabelIngenieríaSpeckle patternsGranular computingReal time synthesisFPGAThis paper introduces Field Programmable Gate Array (FPGA) technology as an alternative platform to implement algorithms for speckle patterns analysis in real time. Functions and algorithmic procedures have been expressed in pseudo languages then in Hardware Description Languages (HDL). For all cases, time performances are presented for the Xilinx Virtex-6 family. Comparisons are also made with PC platform implementations presented in the literature.Sección: Diseño de hardware FPGACentro de Técnicas Analógico-Digitales2011-09info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdf33-38http://sedici.unlp.edu.ar/handle/10915/121411enginfo:eu-repo/semantics/altIdentifier/isbn/978-950-34-0749-3info:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-sa/4.0/Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-29T11:28:49Zoai:sedici.unlp.edu.ar:10915/121411Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-29 11:28:49.579SEDICI (UNLP) - Universidad Nacional de La Platafalse |
dc.title.none.fl_str_mv |
Speckle signal processing through FPGA |
title |
Speckle signal processing through FPGA |
spellingShingle |
Speckle signal processing through FPGA Todorovich, Elías Ingeniería Speckle patterns Granular computing Real time synthesis FPGA |
title_short |
Speckle signal processing through FPGA |
title_full |
Speckle signal processing through FPGA |
title_fullStr |
Speckle signal processing through FPGA |
title_full_unstemmed |
Speckle signal processing through FPGA |
title_sort |
Speckle signal processing through FPGA |
dc.creator.none.fl_str_mv |
Todorovich, Elías Vázquez, Martín Cozzolino, Ezequiel Ferrara, Fernando Bioul, Géry Jean Antoine Dai Para, A. L. Passoni, Lucía Isabel |
author |
Todorovich, Elías |
author_facet |
Todorovich, Elías Vázquez, Martín Cozzolino, Ezequiel Ferrara, Fernando Bioul, Géry Jean Antoine Dai Para, A. L. Passoni, Lucía Isabel |
author_role |
author |
author2 |
Vázquez, Martín Cozzolino, Ezequiel Ferrara, Fernando Bioul, Géry Jean Antoine Dai Para, A. L. Passoni, Lucía Isabel |
author2_role |
author author author author author author |
dc.subject.none.fl_str_mv |
Ingeniería Speckle patterns Granular computing Real time synthesis FPGA |
topic |
Ingeniería Speckle patterns Granular computing Real time synthesis FPGA |
dc.description.none.fl_txt_mv |
This paper introduces Field Programmable Gate Array (FPGA) technology as an alternative platform to implement algorithms for speckle patterns analysis in real time. Functions and algorithmic procedures have been expressed in pseudo languages then in Hardware Description Languages (HDL). For all cases, time performances are presented for the Xilinx Virtex-6 family. Comparisons are also made with PC platform implementations presented in the literature. Sección: Diseño de hardware FPGA Centro de Técnicas Analógico-Digitales |
description |
This paper introduces Field Programmable Gate Array (FPGA) technology as an alternative platform to implement algorithms for speckle patterns analysis in real time. Functions and algorithmic procedures have been expressed in pseudo languages then in Hardware Description Languages (HDL). For all cases, time performances are presented for the Xilinx Virtex-6 family. Comparisons are also made with PC platform implementations presented in the literature. |
publishDate |
2011 |
dc.date.none.fl_str_mv |
2011-09 |
dc.type.none.fl_str_mv |
info:eu-repo/semantics/conferenceObject info:eu-repo/semantics/publishedVersion Objeto de conferencia http://purl.org/coar/resource_type/c_5794 info:ar-repo/semantics/documentoDeConferencia |
format |
conferenceObject |
status_str |
publishedVersion |
dc.identifier.none.fl_str_mv |
http://sedici.unlp.edu.ar/handle/10915/121411 |
url |
http://sedici.unlp.edu.ar/handle/10915/121411 |
dc.language.none.fl_str_mv |
eng |
language |
eng |
dc.relation.none.fl_str_mv |
info:eu-repo/semantics/altIdentifier/isbn/978-950-34-0749-3 |
dc.rights.none.fl_str_mv |
info:eu-repo/semantics/openAccess http://creativecommons.org/licenses/by-nc-sa/4.0/ Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0) |
eu_rights_str_mv |
openAccess |
rights_invalid_str_mv |
http://creativecommons.org/licenses/by-nc-sa/4.0/ Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0) |
dc.format.none.fl_str_mv |
application/pdf 33-38 |
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reponame:SEDICI (UNLP) instname:Universidad Nacional de La Plata instacron:UNLP |
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Universidad Nacional de La Plata |
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SEDICI (UNLP) - Universidad Nacional de La Plata |
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score |
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