FIPBLOX: a graphical interactive design tool for FIPSOC

Autores
Simonelli, Daniel Horacio
Año de publicación
2003
Idioma
inglés
Tipo de recurso
documento de conferencia
Estado
versión publicada
Descripción
FIPSOC is a field programmable mixed-signal integrated device consisting of a Field Programmable Gate Array (FPGA), a set of programmable and interconnectable analog cells, and a microprocessor core which can run general purpose user programs, handle the dynamic reconfiguration of the programmable blocks and probe, in real time, internal digital and analog signals. This device is specially suitable for development and fast prototyping of mixed signal integrated applications. As FIPSOC project is currently under development, it has no yet any powerful tool for synthesis and a structural VHDL (components) approach is to be used for designing. Therefore, the user starts from simple design structures and through a bottom-up style must build more complex components. In this paper we present FIPBLOX, a tool that allows the user automatically generate VHDL code for implementing and customizing high-level modules using the basic resources provided by the FIPSOC FPGA.
Eje: Arquitectura, Redes y Sistemas Operativos (ARSO)
Red de Universidades con Carreras en Informática (RedUNCI)
Materia
Ciencias Informáticas
sistema operativo
Architectures
graphical interactive
FIPBLOX
FIPSOC
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/22644

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network_name_str SEDICI (UNLP)
spelling FIPBLOX: a graphical interactive design tool for FIPSOCSimonelli, Daniel HoracioCiencias Informáticassistema operativoArchitecturesgraphical interactiveFIPBLOXFIPSOCFIPSOC is a field programmable mixed-signal integrated device consisting of a Field Programmable Gate Array (FPGA), a set of programmable and interconnectable analog cells, and a microprocessor core which can run general purpose user programs, handle the dynamic reconfiguration of the programmable blocks and probe, in real time, internal digital and analog signals. This device is specially suitable for development and fast prototyping of mixed signal integrated applications. As FIPSOC project is currently under development, it has no yet any powerful tool for synthesis and a structural VHDL (components) approach is to be used for designing. Therefore, the user starts from simple design structures and through a bottom-up style must build more complex components. In this paper we present FIPBLOX, a tool that allows the user automatically generate VHDL code for implementing and customizing high-level modules using the basic resources provided by the FIPSOC FPGA.Eje: Arquitectura, Redes y Sistemas Operativos (ARSO)Red de Universidades con Carreras en Informática (RedUNCI)2003-10info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdf1373-1383http://sedici.unlp.edu.ar/handle/10915/22644enginfo:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-sa/2.5/ar/Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-29T10:55:07Zoai:sedici.unlp.edu.ar:10915/22644Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-29 10:55:08.097SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv FIPBLOX: a graphical interactive design tool for FIPSOC
title FIPBLOX: a graphical interactive design tool for FIPSOC
spellingShingle FIPBLOX: a graphical interactive design tool for FIPSOC
Simonelli, Daniel Horacio
Ciencias Informáticas
sistema operativo
Architectures
graphical interactive
FIPBLOX
FIPSOC
title_short FIPBLOX: a graphical interactive design tool for FIPSOC
title_full FIPBLOX: a graphical interactive design tool for FIPSOC
title_fullStr FIPBLOX: a graphical interactive design tool for FIPSOC
title_full_unstemmed FIPBLOX: a graphical interactive design tool for FIPSOC
title_sort FIPBLOX: a graphical interactive design tool for FIPSOC
dc.creator.none.fl_str_mv Simonelli, Daniel Horacio
author Simonelli, Daniel Horacio
author_facet Simonelli, Daniel Horacio
author_role author
dc.subject.none.fl_str_mv Ciencias Informáticas
sistema operativo
Architectures
graphical interactive
FIPBLOX
FIPSOC
topic Ciencias Informáticas
sistema operativo
Architectures
graphical interactive
FIPBLOX
FIPSOC
dc.description.none.fl_txt_mv FIPSOC is a field programmable mixed-signal integrated device consisting of a Field Programmable Gate Array (FPGA), a set of programmable and interconnectable analog cells, and a microprocessor core which can run general purpose user programs, handle the dynamic reconfiguration of the programmable blocks and probe, in real time, internal digital and analog signals. This device is specially suitable for development and fast prototyping of mixed signal integrated applications. As FIPSOC project is currently under development, it has no yet any powerful tool for synthesis and a structural VHDL (components) approach is to be used for designing. Therefore, the user starts from simple design structures and through a bottom-up style must build more complex components. In this paper we present FIPBLOX, a tool that allows the user automatically generate VHDL code for implementing and customizing high-level modules using the basic resources provided by the FIPSOC FPGA.
Eje: Arquitectura, Redes y Sistemas Operativos (ARSO)
Red de Universidades con Carreras en Informática (RedUNCI)
description FIPSOC is a field programmable mixed-signal integrated device consisting of a Field Programmable Gate Array (FPGA), a set of programmable and interconnectable analog cells, and a microprocessor core which can run general purpose user programs, handle the dynamic reconfiguration of the programmable blocks and probe, in real time, internal digital and analog signals. This device is specially suitable for development and fast prototyping of mixed signal integrated applications. As FIPSOC project is currently under development, it has no yet any powerful tool for synthesis and a structural VHDL (components) approach is to be used for designing. Therefore, the user starts from simple design structures and through a bottom-up style must build more complex components. In this paper we present FIPBLOX, a tool that allows the user automatically generate VHDL code for implementing and customizing high-level modules using the basic resources provided by the FIPSOC FPGA.
publishDate 2003
dc.date.none.fl_str_mv 2003-10
dc.type.none.fl_str_mv info:eu-repo/semantics/conferenceObject
info:eu-repo/semantics/publishedVersion
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http://purl.org/coar/resource_type/c_5794
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format conferenceObject
status_str publishedVersion
dc.identifier.none.fl_str_mv http://sedici.unlp.edu.ar/handle/10915/22644
url http://sedici.unlp.edu.ar/handle/10915/22644
dc.language.none.fl_str_mv eng
language eng
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
dc.format.none.fl_str_mv application/pdf
1373-1383
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