Improving the computational efficiency of lock-in algorithms through coherent averaging

Autores
Oliva, Matias Javier; Veiga, Alejandro Luis; Arias García, Pablo Andrés; Spinelli, Enrique Mario
Año de publicación
2024
Idioma
inglés
Tipo de recurso
artículo
Estado
versión publicada
Descripción
The lock-in amplifier is a commonly used technique for the processing of noisy signals with a known periodicity that involves multiplying the signal with one or more reference signals of the same periodicity and low-pass filtering the results. This enables the recovery of the amplitude and phase of the signal being measured. Another well studied technique to reduce the noise of periodic signals is the coherent averaging method, where the samples of a noisy signal with a known periodicity are averaged coherently. In this paper, a novel system combining both algorithms is proposed. In this approach, the signal is first averaged coherently for a number of cycles (Nca) and then passed through a conventional lock-in with a moving average filter of a whole number of periods of the signal (Nma) as a lowpass filter. In this scenario, the question of how to distribute the incoming samples between the coherent average and the conventional lock-in scheme arises. The mathematical aspects of this issue were evaluated, leading to the conclusion that the calculation results remain identical as long as the product NcaNma remains constant. However, it was observed that the number of operations required for each algorithm varies. By maximizing the number of samples used for the coherent average, the number of multiplications involved can be drastically reduced from NcaNmaM to just M, where M represents the number of samples in a single period of the signal. The drawbacks are the need for space to store the averaged signal, a slower convergence to the result, and an extra cycle in the calculations. Any lockin system with moving average filter can take advantage of these results. Particularly in this study, they are employed to nearly double the achievable clock frequency of a lock-in system implemented on a Cyclone V FPGA, taking it from 119.39 MHz to 216.54 MHz without the use of hardware embedded multipliers.
Fil: Oliva, Matias Javier. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; Argentina
Fil: Veiga, Alejandro Luis. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; Argentina
Fil: Arias García, Pablo Andrés. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; Argentina
Fil: Spinelli, Enrique Mario. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; Argentina
Materia
Lock-in
Coherent average
Computational efficiency
Digital Signal Processing
Nivel de accesibilidad
acceso abierto
Condiciones de uso
https://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Repositorio
CONICET Digital (CONICET)
Institución
Consejo Nacional de Investigaciones Científicas y Técnicas
OAI Identificador
oai:ri.conicet.gov.ar:11336/262769
Acceder
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oai_identifier_str oai:ri.conicet.gov.ar:11336/262769
network_acronym_str CONICETDig
repository_id_str 3498
network_name_str CONICET Digital (CONICET)
spelling Improving the computational efficiency of lock-in algorithms through coherent averagingOliva, Matias JavierVeiga, Alejandro LuisArias García, Pablo AndrésSpinelli, Enrique MarioLock-inCoherent averageComputational efficiencyDigital Signal Processinghttps://purl.org/becyt/ford/2.2https://purl.org/becyt/ford/2The lock-in amplifier is a commonly used technique for the processing of noisy signals with a known periodicity that involves multiplying the signal with one or more reference signals of the same periodicity and low-pass filtering the results. This enables the recovery of the amplitude and phase of the signal being measured. Another well studied technique to reduce the noise of periodic signals is the coherent averaging method, where the samples of a noisy signal with a known periodicity are averaged coherently. In this paper, a novel system combining both algorithms is proposed. In this approach, the signal is first averaged coherently for a number of cycles (Nca) and then passed through a conventional lock-in with a moving average filter of a whole number of periods of the signal (Nma) as a lowpass filter. In this scenario, the question of how to distribute the incoming samples between the coherent average and the conventional lock-in scheme arises. The mathematical aspects of this issue were evaluated, leading to the conclusion that the calculation results remain identical as long as the product NcaNma remains constant. However, it was observed that the number of operations required for each algorithm varies. By maximizing the number of samples used for the coherent average, the number of multiplications involved can be drastically reduced from NcaNmaM to just M, where M represents the number of samples in a single period of the signal. The drawbacks are the need for space to store the averaged signal, a slower convergence to the result, and an extra cycle in the calculations. Any lockin system with moving average filter can take advantage of these results. Particularly in this study, they are employed to nearly double the achievable clock frequency of a lock-in system implemented on a Cyclone V FPGA, taking it from 119.39 MHz to 216.54 MHz without the use of hardware embedded multipliers.Fil: Oliva, Matias Javier. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; ArgentinaFil: Veiga, Alejandro Luis. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; ArgentinaFil: Arias García, Pablo Andrés. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; ArgentinaFil: Spinelli, Enrique Mario. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; ArgentinaAcademic Press Inc Elsevier Science2024-07info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionhttp://purl.org/coar/resource_type/c_6501info:ar-repo/semantics/articuloapplication/pdfapplication/pdfapplication/pdfhttp://hdl.handle.net/11336/262769Oliva, Matias Javier; Veiga, Alejandro Luis; Arias García, Pablo Andrés; Spinelli, Enrique Mario; Improving the computational efficiency of lock-in algorithms through coherent averaging; Academic Press Inc Elsevier Science; Digital Signal Processing; 154; 104693; 7-2024; 1-101051-2004CONICET DigitalCONICETenginfo:eu-repo/semantics/altIdentifier/url/https://linkinghub.elsevier.com/retrieve/pii/S105120042400318Xinfo:eu-repo/semantics/altIdentifier/doi/10.1016/j.dsp.2024.104693info:eu-repo/semantics/openAccesshttps://creativecommons.org/licenses/by-nc-sa/2.5/ar/reponame:CONICET Digital (CONICET)instname:Consejo Nacional de Investigaciones Científicas y Técnicas2025-09-03T10:03:36Zoai:ri.conicet.gov.ar:11336/262769instacron:CONICETInstitucionalhttp://ri.conicet.gov.ar/Organismo científico-tecnológicoNo correspondehttp://ri.conicet.gov.ar/oai/requestdasensio@conicet.gov.ar; lcarlino@conicet.gov.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:34982025-09-03 10:03:36.379CONICET Digital (CONICET) - Consejo Nacional de Investigaciones Científicas y Técnicasfalse
dc.title.none.fl_str_mv Improving the computational efficiency of lock-in algorithms through coherent averaging
title Improving the computational efficiency of lock-in algorithms through coherent averaging
spellingShingle Improving the computational efficiency of lock-in algorithms through coherent averaging
Oliva, Matias Javier
Lock-in
Coherent average
Computational efficiency
Digital Signal Processing
title_short Improving the computational efficiency of lock-in algorithms through coherent averaging
title_full Improving the computational efficiency of lock-in algorithms through coherent averaging
title_fullStr Improving the computational efficiency of lock-in algorithms through coherent averaging
title_full_unstemmed Improving the computational efficiency of lock-in algorithms through coherent averaging
title_sort Improving the computational efficiency of lock-in algorithms through coherent averaging
dc.creator.none.fl_str_mv Oliva, Matias Javier
Veiga, Alejandro Luis
Arias García, Pablo Andrés
Spinelli, Enrique Mario
author Oliva, Matias Javier
author_facet Oliva, Matias Javier
Veiga, Alejandro Luis
Arias García, Pablo Andrés
Spinelli, Enrique Mario
author_role author
author2 Veiga, Alejandro Luis
Arias García, Pablo Andrés
Spinelli, Enrique Mario
author2_role author
author
author
dc.subject.none.fl_str_mv Lock-in
Coherent average
Computational efficiency
Digital Signal Processing
topic Lock-in
Coherent average
Computational efficiency
Digital Signal Processing
purl_subject.fl_str_mv https://purl.org/becyt/ford/2.2
https://purl.org/becyt/ford/2
dc.description.none.fl_txt_mv The lock-in amplifier is a commonly used technique for the processing of noisy signals with a known periodicity that involves multiplying the signal with one or more reference signals of the same periodicity and low-pass filtering the results. This enables the recovery of the amplitude and phase of the signal being measured. Another well studied technique to reduce the noise of periodic signals is the coherent averaging method, where the samples of a noisy signal with a known periodicity are averaged coherently. In this paper, a novel system combining both algorithms is proposed. In this approach, the signal is first averaged coherently for a number of cycles (Nca) and then passed through a conventional lock-in with a moving average filter of a whole number of periods of the signal (Nma) as a lowpass filter. In this scenario, the question of how to distribute the incoming samples between the coherent average and the conventional lock-in scheme arises. The mathematical aspects of this issue were evaluated, leading to the conclusion that the calculation results remain identical as long as the product NcaNma remains constant. However, it was observed that the number of operations required for each algorithm varies. By maximizing the number of samples used for the coherent average, the number of multiplications involved can be drastically reduced from NcaNmaM to just M, where M represents the number of samples in a single period of the signal. The drawbacks are the need for space to store the averaged signal, a slower convergence to the result, and an extra cycle in the calculations. Any lockin system with moving average filter can take advantage of these results. Particularly in this study, they are employed to nearly double the achievable clock frequency of a lock-in system implemented on a Cyclone V FPGA, taking it from 119.39 MHz to 216.54 MHz without the use of hardware embedded multipliers.
Fil: Oliva, Matias Javier. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; Argentina
Fil: Veiga, Alejandro Luis. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; Argentina
Fil: Arias García, Pablo Andrés. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; Argentina
Fil: Spinelli, Enrique Mario. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; Argentina
description The lock-in amplifier is a commonly used technique for the processing of noisy signals with a known periodicity that involves multiplying the signal with one or more reference signals of the same periodicity and low-pass filtering the results. This enables the recovery of the amplitude and phase of the signal being measured. Another well studied technique to reduce the noise of periodic signals is the coherent averaging method, where the samples of a noisy signal with a known periodicity are averaged coherently. In this paper, a novel system combining both algorithms is proposed. In this approach, the signal is first averaged coherently for a number of cycles (Nca) and then passed through a conventional lock-in with a moving average filter of a whole number of periods of the signal (Nma) as a lowpass filter. In this scenario, the question of how to distribute the incoming samples between the coherent average and the conventional lock-in scheme arises. The mathematical aspects of this issue were evaluated, leading to the conclusion that the calculation results remain identical as long as the product NcaNma remains constant. However, it was observed that the number of operations required for each algorithm varies. By maximizing the number of samples used for the coherent average, the number of multiplications involved can be drastically reduced from NcaNmaM to just M, where M represents the number of samples in a single period of the signal. The drawbacks are the need for space to store the averaged signal, a slower convergence to the result, and an extra cycle in the calculations. Any lockin system with moving average filter can take advantage of these results. Particularly in this study, they are employed to nearly double the achievable clock frequency of a lock-in system implemented on a Cyclone V FPGA, taking it from 119.39 MHz to 216.54 MHz without the use of hardware embedded multipliers.
publishDate 2024
dc.date.none.fl_str_mv 2024-07
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
http://purl.org/coar/resource_type/c_6501
info:ar-repo/semantics/articulo
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv http://hdl.handle.net/11336/262769
Oliva, Matias Javier; Veiga, Alejandro Luis; Arias García, Pablo Andrés; Spinelli, Enrique Mario; Improving the computational efficiency of lock-in algorithms through coherent averaging; Academic Press Inc Elsevier Science; Digital Signal Processing; 154; 104693; 7-2024; 1-10
1051-2004
CONICET Digital
CONICET
url http://hdl.handle.net/11336/262769
identifier_str_mv Oliva, Matias Javier; Veiga, Alejandro Luis; Arias García, Pablo Andrés; Spinelli, Enrique Mario; Improving the computational efficiency of lock-in algorithms through coherent averaging; Academic Press Inc Elsevier Science; Digital Signal Processing; 154; 104693; 7-2024; 1-10
1051-2004
CONICET Digital
CONICET
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv info:eu-repo/semantics/altIdentifier/url/https://linkinghub.elsevier.com/retrieve/pii/S105120042400318X
info:eu-repo/semantics/altIdentifier/doi/10.1016/j.dsp.2024.104693
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
https://creativecommons.org/licenses/by-nc-sa/2.5/ar/
eu_rights_str_mv openAccess
rights_invalid_str_mv https://creativecommons.org/licenses/by-nc-sa/2.5/ar/
dc.format.none.fl_str_mv application/pdf
application/pdf
application/pdf
dc.publisher.none.fl_str_mv Academic Press Inc Elsevier Science
publisher.none.fl_str_mv Academic Press Inc Elsevier Science
dc.source.none.fl_str_mv reponame:CONICET Digital (CONICET)
instname:Consejo Nacional de Investigaciones Científicas y Técnicas
reponame_str CONICET Digital (CONICET)
collection CONICET Digital (CONICET)
instname_str Consejo Nacional de Investigaciones Científicas y Técnicas
repository.name.fl_str_mv CONICET Digital (CONICET) - Consejo Nacional de Investigaciones Científicas y Técnicas
repository.mail.fl_str_mv dasensio@conicet.gov.ar; lcarlino@conicet.gov.ar
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