Building a Fab on a Chip

Autores
Imboden, Matthias; Han, Han; Stark, Thomas; Lowell, Evan; Chang, Jackson; Pardo, Flavio; Bolle, Cristian; del Corro, Pablo Guillermo; Bishop, David J.
Año de publicación
2014
Idioma
inglés
Tipo de recurso
artículo
Estado
versión publicada
Descripción
Semiconductor fabs are large, complex industrial sites with costs for a single facility approaching $10B. In this paper we discuss the possibility of putting the entire functionality of such a fab onto a single silicon chip. We demonstrate a path forward where, for certain applications, especially at the nanometer scale, one can consider using a single chip approach for building devices with significant potential cost savings. In our approach, we build micro versions of the macro machines one typically finds in a fab, and integrating all the components together. We argue that the technology now exists to allow one to build a Fab on a Chip.
Fil: Imboden, Matthias. Boston University; Estados Unidos
Fil: Han, Han. Boston University; Estados Unidos
Fil: Stark, Thomas. Boston University; Estados Unidos
Fil: Lowell, Evan. Boston University; Estados Unidos
Fil: Chang, Jackson. Boston University; Estados Unidos
Fil: Pardo, Flavio. Bell Labs; Estados Unidos
Fil: Bolle, Cristian. Bell Labs; Estados Unidos
Fil: del Corro, Pablo Guillermo. Comisión Nacional de Energía Atómica. Centro Atómico Bariloche; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina
Fil: Bishop, David J.. Boston University; Estados Unidos
Materia
Mems
Foc
Nivel de accesibilidad
acceso abierto
Condiciones de uso
https://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Repositorio
CONICET Digital (CONICET)
Institución
Consejo Nacional de Investigaciones Científicas y Técnicas
OAI Identificador
oai:ri.conicet.gov.ar:11336/34219

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spelling Building a Fab on a ChipImboden, MatthiasHan, HanStark, ThomasLowell, EvanChang, JacksonPardo, FlavioBolle, Cristiandel Corro, Pablo GuillermoBishop, David J.MemsFochttps://purl.org/becyt/ford/2.10https://purl.org/becyt/ford/2Semiconductor fabs are large, complex industrial sites with costs for a single facility approaching $10B. In this paper we discuss the possibility of putting the entire functionality of such a fab onto a single silicon chip. We demonstrate a path forward where, for certain applications, especially at the nanometer scale, one can consider using a single chip approach for building devices with significant potential cost savings. In our approach, we build micro versions of the macro machines one typically finds in a fab, and integrating all the components together. We argue that the technology now exists to allow one to build a Fab on a Chip.Fil: Imboden, Matthias. Boston University; Estados UnidosFil: Han, Han. Boston University; Estados UnidosFil: Stark, Thomas. Boston University; Estados UnidosFil: Lowell, Evan. Boston University; Estados UnidosFil: Chang, Jackson. Boston University; Estados UnidosFil: Pardo, Flavio. Bell Labs; Estados UnidosFil: Bolle, Cristian. Bell Labs; Estados UnidosFil: del Corro, Pablo Guillermo. Comisión Nacional de Energía Atómica. Centro Atómico Bariloche; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Bishop, David J.. Boston University; Estados UnidosRoyal Society of Chemistry2014-04info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionhttp://purl.org/coar/resource_type/c_6501info:ar-repo/semantics/articuloapplication/pdfapplication/pdfapplication/pdfhttp://hdl.handle.net/11336/34219Imboden, Matthias; Han, Han; Stark, Thomas; Lowell, Evan; Chang, Jackson; et al.; Building a Fab on a Chip; Royal Society of Chemistry; Nanoscale; 6; 10; 4-2014; 5049-50622040-3364CONICET DigitalCONICETenginfo:eu-repo/semantics/altIdentifier/doi/10.1039/C3NR06087Jinfo:eu-repo/semantics/altIdentifier/url/http://pubs.rsc.org/en/Content/ArticleLanding/2014/NR/C3NR06087Jinfo:eu-repo/semantics/openAccesshttps://creativecommons.org/licenses/by-nc-sa/2.5/ar/reponame:CONICET Digital (CONICET)instname:Consejo Nacional de Investigaciones Científicas y Técnicas2025-09-03T09:44:48Zoai:ri.conicet.gov.ar:11336/34219instacron:CONICETInstitucionalhttp://ri.conicet.gov.ar/Organismo científico-tecnológicoNo correspondehttp://ri.conicet.gov.ar/oai/requestdasensio@conicet.gov.ar; lcarlino@conicet.gov.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:34982025-09-03 09:44:49.129CONICET Digital (CONICET) - Consejo Nacional de Investigaciones Científicas y Técnicasfalse
dc.title.none.fl_str_mv Building a Fab on a Chip
title Building a Fab on a Chip
spellingShingle Building a Fab on a Chip
Imboden, Matthias
Mems
Foc
title_short Building a Fab on a Chip
title_full Building a Fab on a Chip
title_fullStr Building a Fab on a Chip
title_full_unstemmed Building a Fab on a Chip
title_sort Building a Fab on a Chip
dc.creator.none.fl_str_mv Imboden, Matthias
Han, Han
Stark, Thomas
Lowell, Evan
Chang, Jackson
Pardo, Flavio
Bolle, Cristian
del Corro, Pablo Guillermo
Bishop, David J.
author Imboden, Matthias
author_facet Imboden, Matthias
Han, Han
Stark, Thomas
Lowell, Evan
Chang, Jackson
Pardo, Flavio
Bolle, Cristian
del Corro, Pablo Guillermo
Bishop, David J.
author_role author
author2 Han, Han
Stark, Thomas
Lowell, Evan
Chang, Jackson
Pardo, Flavio
Bolle, Cristian
del Corro, Pablo Guillermo
Bishop, David J.
author2_role author
author
author
author
author
author
author
author
dc.subject.none.fl_str_mv Mems
Foc
topic Mems
Foc
purl_subject.fl_str_mv https://purl.org/becyt/ford/2.10
https://purl.org/becyt/ford/2
dc.description.none.fl_txt_mv Semiconductor fabs are large, complex industrial sites with costs for a single facility approaching $10B. In this paper we discuss the possibility of putting the entire functionality of such a fab onto a single silicon chip. We demonstrate a path forward where, for certain applications, especially at the nanometer scale, one can consider using a single chip approach for building devices with significant potential cost savings. In our approach, we build micro versions of the macro machines one typically finds in a fab, and integrating all the components together. We argue that the technology now exists to allow one to build a Fab on a Chip.
Fil: Imboden, Matthias. Boston University; Estados Unidos
Fil: Han, Han. Boston University; Estados Unidos
Fil: Stark, Thomas. Boston University; Estados Unidos
Fil: Lowell, Evan. Boston University; Estados Unidos
Fil: Chang, Jackson. Boston University; Estados Unidos
Fil: Pardo, Flavio. Bell Labs; Estados Unidos
Fil: Bolle, Cristian. Bell Labs; Estados Unidos
Fil: del Corro, Pablo Guillermo. Comisión Nacional de Energía Atómica. Centro Atómico Bariloche; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina
Fil: Bishop, David J.. Boston University; Estados Unidos
description Semiconductor fabs are large, complex industrial sites with costs for a single facility approaching $10B. In this paper we discuss the possibility of putting the entire functionality of such a fab onto a single silicon chip. We demonstrate a path forward where, for certain applications, especially at the nanometer scale, one can consider using a single chip approach for building devices with significant potential cost savings. In our approach, we build micro versions of the macro machines one typically finds in a fab, and integrating all the components together. We argue that the technology now exists to allow one to build a Fab on a Chip.
publishDate 2014
dc.date.none.fl_str_mv 2014-04
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
http://purl.org/coar/resource_type/c_6501
info:ar-repo/semantics/articulo
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv http://hdl.handle.net/11336/34219
Imboden, Matthias; Han, Han; Stark, Thomas; Lowell, Evan; Chang, Jackson; et al.; Building a Fab on a Chip; Royal Society of Chemistry; Nanoscale; 6; 10; 4-2014; 5049-5062
2040-3364
CONICET Digital
CONICET
url http://hdl.handle.net/11336/34219
identifier_str_mv Imboden, Matthias; Han, Han; Stark, Thomas; Lowell, Evan; Chang, Jackson; et al.; Building a Fab on a Chip; Royal Society of Chemistry; Nanoscale; 6; 10; 4-2014; 5049-5062
2040-3364
CONICET Digital
CONICET
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv info:eu-repo/semantics/altIdentifier/doi/10.1039/C3NR06087J
info:eu-repo/semantics/altIdentifier/url/http://pubs.rsc.org/en/Content/ArticleLanding/2014/NR/C3NR06087J
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
https://creativecommons.org/licenses/by-nc-sa/2.5/ar/
eu_rights_str_mv openAccess
rights_invalid_str_mv https://creativecommons.org/licenses/by-nc-sa/2.5/ar/
dc.format.none.fl_str_mv application/pdf
application/pdf
application/pdf
dc.publisher.none.fl_str_mv Royal Society of Chemistry
publisher.none.fl_str_mv Royal Society of Chemistry
dc.source.none.fl_str_mv reponame:CONICET Digital (CONICET)
instname:Consejo Nacional de Investigaciones Científicas y Técnicas
reponame_str CONICET Digital (CONICET)
collection CONICET Digital (CONICET)
instname_str Consejo Nacional de Investigaciones Científicas y Técnicas
repository.name.fl_str_mv CONICET Digital (CONICET) - Consejo Nacional de Investigaciones Científicas y Técnicas
repository.mail.fl_str_mv dasensio@conicet.gov.ar; lcarlino@conicet.gov.ar
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