FPGA-Based Digital filters using Bit-Serial arithmetic

Autores
Arroyuelo, Mónica; Arroyuelo, Jorge; Grosso, Alejandro
Año de publicación
2007
Idioma
español castellano
Tipo de recurso
documento de conferencia
Estado
versión publicada
Descripción
This paper presents an efficient method for implementation of digital filters targeted FPGA architectures. The traditional approach is based on application of general purpose multipliers. However, multipliers implemented in FPGA architectures do not allow to construct economic Digital Filters. For this reason, multipliers are replaced by Lookup Tables and Adder-Substractor, which use Bit-Serial Arithmetic. Lookup Tables can be of considerable size in high order filters, thus interconnection techniques will be used to construct high order filters from a set of low order filters. The paper presents several examples confirming that these techniques allow a reduction in logic cells utilization of filters implementation based on Bit-Serial Arithmetic concept.
II Workshop de Arquitecturas, Redes y Sistemas Operativos
Red de Universidades con Carreras en Informática (RedUNCI)
Materia
Ciencias Informáticas
Informática
Information filtering
Filtering
digital filter
FIR-Filter
IIR-Filter
lookup tables
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/21693
Acceder
id SEDICI_c7964710250f9e8586abdc687d62e332
oai_identifier_str oai:sedici.unlp.edu.ar:10915/21693
network_acronym_str SEDICI
repository_id_str 1329
network_name_str SEDICI (UNLP)
spelling FPGA-Based Digital filters using Bit-Serial arithmeticArroyuelo, MónicaArroyuelo, JorgeGrosso, AlejandroCiencias InformáticasInformáticaInformation filteringFilteringdigital filterFIR-FilterIIR-Filterlookup tablesThis paper presents an efficient method for implementation of digital filters targeted FPGA architectures. The traditional approach is based on application of general purpose multipliers. However, multipliers implemented in FPGA architectures do not allow to construct economic Digital Filters. For this reason, multipliers are replaced by Lookup Tables and Adder-Substractor, which use Bit-Serial Arithmetic. Lookup Tables can be of considerable size in high order filters, thus interconnection techniques will be used to construct high order filters from a set of low order filters. The paper presents several examples confirming that these techniques allow a reduction in logic cells utilization of filters implementation based on Bit-Serial Arithmetic concept.II Workshop de Arquitecturas, Redes y Sistemas OperativosRed de Universidades con Carreras en Informática (RedUNCI)2007info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdf113-123http://sedici.unlp.edu.ar/handle/10915/21693spainfo:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-sa/2.5/ar/Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-10-22T16:36:18Zoai:sedici.unlp.edu.ar:10915/21693Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-10-22 16:36:18.956SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv FPGA-Based Digital filters using Bit-Serial arithmetic
title FPGA-Based Digital filters using Bit-Serial arithmetic
spellingShingle FPGA-Based Digital filters using Bit-Serial arithmetic
Arroyuelo, Mónica
Ciencias Informáticas
Informática
Information filtering
Filtering
digital filter
FIR-Filter
IIR-Filter
lookup tables
title_short FPGA-Based Digital filters using Bit-Serial arithmetic
title_full FPGA-Based Digital filters using Bit-Serial arithmetic
title_fullStr FPGA-Based Digital filters using Bit-Serial arithmetic
title_full_unstemmed FPGA-Based Digital filters using Bit-Serial arithmetic
title_sort FPGA-Based Digital filters using Bit-Serial arithmetic
dc.creator.none.fl_str_mv Arroyuelo, Mónica
Arroyuelo, Jorge
Grosso, Alejandro
author Arroyuelo, Mónica
author_facet Arroyuelo, Mónica
Arroyuelo, Jorge
Grosso, Alejandro
author_role author
author2 Arroyuelo, Jorge
Grosso, Alejandro
author2_role author
author
dc.subject.none.fl_str_mv Ciencias Informáticas
Informática
Information filtering
Filtering
digital filter
FIR-Filter
IIR-Filter
lookup tables
topic Ciencias Informáticas
Informática
Information filtering
Filtering
digital filter
FIR-Filter
IIR-Filter
lookup tables
dc.description.none.fl_txt_mv This paper presents an efficient method for implementation of digital filters targeted FPGA architectures. The traditional approach is based on application of general purpose multipliers. However, multipliers implemented in FPGA architectures do not allow to construct economic Digital Filters. For this reason, multipliers are replaced by Lookup Tables and Adder-Substractor, which use Bit-Serial Arithmetic. Lookup Tables can be of considerable size in high order filters, thus interconnection techniques will be used to construct high order filters from a set of low order filters. The paper presents several examples confirming that these techniques allow a reduction in logic cells utilization of filters implementation based on Bit-Serial Arithmetic concept.
II Workshop de Arquitecturas, Redes y Sistemas Operativos
Red de Universidades con Carreras en Informática (RedUNCI)
description This paper presents an efficient method for implementation of digital filters targeted FPGA architectures. The traditional approach is based on application of general purpose multipliers. However, multipliers implemented in FPGA architectures do not allow to construct economic Digital Filters. For this reason, multipliers are replaced by Lookup Tables and Adder-Substractor, which use Bit-Serial Arithmetic. Lookup Tables can be of considerable size in high order filters, thus interconnection techniques will be used to construct high order filters from a set of low order filters. The paper presents several examples confirming that these techniques allow a reduction in logic cells utilization of filters implementation based on Bit-Serial Arithmetic concept.
publishDate 2007
dc.date.none.fl_str_mv 2007
dc.type.none.fl_str_mv info:eu-repo/semantics/conferenceObject
info:eu-repo/semantics/publishedVersion
Objeto de conferencia
http://purl.org/coar/resource_type/c_5794
info:ar-repo/semantics/documentoDeConferencia
format conferenceObject
status_str publishedVersion
dc.identifier.none.fl_str_mv http://sedici.unlp.edu.ar/handle/10915/21693
url http://sedici.unlp.edu.ar/handle/10915/21693
dc.language.none.fl_str_mv spa
language spa
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
dc.format.none.fl_str_mv application/pdf
113-123
dc.source.none.fl_str_mv reponame:SEDICI (UNLP)
instname:Universidad Nacional de La Plata
instacron:UNLP
reponame_str SEDICI (UNLP)
collection SEDICI (UNLP)
instname_str Universidad Nacional de La Plata
instacron_str UNLP
institution UNLP
repository.name.fl_str_mv SEDICI (UNLP) - Universidad Nacional de La Plata
repository.mail.fl_str_mv alira@sedici.unlp.edu.ar
_version_ 1846782816615923712
score 12.982451

Publicaciones similares