Interface PCI para PC compatible
- Autores
- Micolini, Orlando; Damiani, Adriana; Gamarra, Leonardo; Ventre, Luis O.
- Año de publicación
- 2007
- Idioma
- español castellano
- Tipo de recurso
- documento de conferencia
- Estado
- versión publicada
- Descripción
- We call BUS to any group of lines whose main purpose its interconnect different devices. One of the most critical problem in digital aplicattions its to establish a fast access communication between peripheral devices. With the intention of diminishing the limitations in the data transfer rate, in year 1992, Intel develops the Standard bus of interconnection of peripheral components (PCI). The PCI Bus, is the most used standard for the development of aplication where work togheter external components to the CPU; this paper discuss the development of my end career project, which raises the implementation of a CORE, intrument that allows to fulfill the highest requirements of the communication protocol PCI, this instrument is implemented on a reprogrammable logic FPGA Board. Also, explain the implement of drivers for testing the development under an operating system, and several visual aplications were created to validate the communication and bidirectional data transfer. At the end of this paper, we measured and studied the results to specify the reasons that allows us to affirm that the development is successful.
II Workshop de Arquitecturas, Redes y Sistemas Operativos
Red de Universidades con Carreras en Informática (RedUNCI) - Materia
-
Ciencias Informáticas
Informática
computer architecture
PCI Bus
FPGA
System architectures
Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)
Peripheral control - Nivel de accesibilidad
- acceso abierto
- Condiciones de uso
- http://creativecommons.org/licenses/by-nc-sa/2.5/ar/
- Repositorio
- Institución
- Universidad Nacional de La Plata
- OAI Identificador
- oai:sedici.unlp.edu.ar:10915/21700
Ver los metadatos del registro completo
id |
SEDICI_9949cc23b082c54408b59907197a3c0a |
---|---|
oai_identifier_str |
oai:sedici.unlp.edu.ar:10915/21700 |
network_acronym_str |
SEDICI |
repository_id_str |
1329 |
network_name_str |
SEDICI (UNLP) |
spelling |
Interface PCI para PC compatibleMicolini, OrlandoDamiani, AdrianaGamarra, LeonardoVentre, Luis O.Ciencias InformáticasInformáticacomputer architecturePCI BusFPGASystem architecturesInterconnection architectures (e.g., common bus, multiport memory, crossbar switch)Peripheral controlWe call BUS to any group of lines whose main purpose its interconnect different devices. One of the most critical problem in digital aplicattions its to establish a fast access communication between peripheral devices. With the intention of diminishing the limitations in the data transfer rate, in year 1992, Intel develops the Standard bus of interconnection of peripheral components (PCI). The PCI Bus, is the most used standard for the development of aplication where work togheter external components to the CPU; this paper discuss the development of my end career project, which raises the implementation of a CORE, intrument that allows to fulfill the highest requirements of the communication protocol PCI, this instrument is implemented on a reprogrammable logic FPGA Board. Also, explain the implement of drivers for testing the development under an operating system, and several visual aplications were created to validate the communication and bidirectional data transfer. At the end of this paper, we measured and studied the results to specify the reasons that allows us to affirm that the development is successful.II Workshop de Arquitecturas, Redes y Sistemas OperativosRed de Universidades con Carreras en Informática (RedUNCI)2007info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdf159-168http://sedici.unlp.edu.ar/handle/10915/21700spainfo:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-sa/2.5/ar/Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-29T10:54:43Zoai:sedici.unlp.edu.ar:10915/21700Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-29 10:54:43.436SEDICI (UNLP) - Universidad Nacional de La Platafalse |
dc.title.none.fl_str_mv |
Interface PCI para PC compatible |
title |
Interface PCI para PC compatible |
spellingShingle |
Interface PCI para PC compatible Micolini, Orlando Ciencias Informáticas Informática computer architecture PCI Bus FPGA System architectures Interconnection architectures (e.g., common bus, multiport memory, crossbar switch) Peripheral control |
title_short |
Interface PCI para PC compatible |
title_full |
Interface PCI para PC compatible |
title_fullStr |
Interface PCI para PC compatible |
title_full_unstemmed |
Interface PCI para PC compatible |
title_sort |
Interface PCI para PC compatible |
dc.creator.none.fl_str_mv |
Micolini, Orlando Damiani, Adriana Gamarra, Leonardo Ventre, Luis O. |
author |
Micolini, Orlando |
author_facet |
Micolini, Orlando Damiani, Adriana Gamarra, Leonardo Ventre, Luis O. |
author_role |
author |
author2 |
Damiani, Adriana Gamarra, Leonardo Ventre, Luis O. |
author2_role |
author author author |
dc.subject.none.fl_str_mv |
Ciencias Informáticas Informática computer architecture PCI Bus FPGA System architectures Interconnection architectures (e.g., common bus, multiport memory, crossbar switch) Peripheral control |
topic |
Ciencias Informáticas Informática computer architecture PCI Bus FPGA System architectures Interconnection architectures (e.g., common bus, multiport memory, crossbar switch) Peripheral control |
dc.description.none.fl_txt_mv |
We call BUS to any group of lines whose main purpose its interconnect different devices. One of the most critical problem in digital aplicattions its to establish a fast access communication between peripheral devices. With the intention of diminishing the limitations in the data transfer rate, in year 1992, Intel develops the Standard bus of interconnection of peripheral components (PCI). The PCI Bus, is the most used standard for the development of aplication where work togheter external components to the CPU; this paper discuss the development of my end career project, which raises the implementation of a CORE, intrument that allows to fulfill the highest requirements of the communication protocol PCI, this instrument is implemented on a reprogrammable logic FPGA Board. Also, explain the implement of drivers for testing the development under an operating system, and several visual aplications were created to validate the communication and bidirectional data transfer. At the end of this paper, we measured and studied the results to specify the reasons that allows us to affirm that the development is successful. II Workshop de Arquitecturas, Redes y Sistemas Operativos Red de Universidades con Carreras en Informática (RedUNCI) |
description |
We call BUS to any group of lines whose main purpose its interconnect different devices. One of the most critical problem in digital aplicattions its to establish a fast access communication between peripheral devices. With the intention of diminishing the limitations in the data transfer rate, in year 1992, Intel develops the Standard bus of interconnection of peripheral components (PCI). The PCI Bus, is the most used standard for the development of aplication where work togheter external components to the CPU; this paper discuss the development of my end career project, which raises the implementation of a CORE, intrument that allows to fulfill the highest requirements of the communication protocol PCI, this instrument is implemented on a reprogrammable logic FPGA Board. Also, explain the implement of drivers for testing the development under an operating system, and several visual aplications were created to validate the communication and bidirectional data transfer. At the end of this paper, we measured and studied the results to specify the reasons that allows us to affirm that the development is successful. |
publishDate |
2007 |
dc.date.none.fl_str_mv |
2007 |
dc.type.none.fl_str_mv |
info:eu-repo/semantics/conferenceObject info:eu-repo/semantics/publishedVersion Objeto de conferencia http://purl.org/coar/resource_type/c_5794 info:ar-repo/semantics/documentoDeConferencia |
format |
conferenceObject |
status_str |
publishedVersion |
dc.identifier.none.fl_str_mv |
http://sedici.unlp.edu.ar/handle/10915/21700 |
url |
http://sedici.unlp.edu.ar/handle/10915/21700 |
dc.language.none.fl_str_mv |
spa |
language |
spa |
dc.rights.none.fl_str_mv |
info:eu-repo/semantics/openAccess http://creativecommons.org/licenses/by-nc-sa/2.5/ar/ Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5) |
eu_rights_str_mv |
openAccess |
rights_invalid_str_mv |
http://creativecommons.org/licenses/by-nc-sa/2.5/ar/ Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5) |
dc.format.none.fl_str_mv |
application/pdf 159-168 |
dc.source.none.fl_str_mv |
reponame:SEDICI (UNLP) instname:Universidad Nacional de La Plata instacron:UNLP |
reponame_str |
SEDICI (UNLP) |
collection |
SEDICI (UNLP) |
instname_str |
Universidad Nacional de La Plata |
instacron_str |
UNLP |
institution |
UNLP |
repository.name.fl_str_mv |
SEDICI (UNLP) - Universidad Nacional de La Plata |
repository.mail.fl_str_mv |
alira@sedici.unlp.edu.ar |
_version_ |
1844615805514285056 |
score |
13.070432 |