Fault tolerance in an amplifier system implemented in reconfigurable system on chip platform

Autores
Lovay, Mónica; Peretti, Gabriela; Romero, Eduardo; Marqués, Carlos
Año de publicación
2011
Idioma
inglés
Tipo de recurso
documento de conferencia
Estado
versión publicada
Descripción
This work address the problem of providing fault tolerance to an analog system embedded in a commercial programmable system on chip. The system presents a functionality that has to be maintained despite the presence of faults, without direct human intervention. For detecting a gain fault, we use a built-in self-test strategy that establishes the actual values of gain achievable by the system. A simulated annealing (SA) algorithm finds the hardware configuration. The simulation results show that the strategy is able to maintain its functionality under the presence of catastrophic and deviation faults. In addition, SA presents better performance than an exhaustive search method.
Centro de Técnicas Analógico-Digitales
Materia
Ingeniería
Hardware fault tolerance
Amplifier system
Simulated annealing algorithm
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by-nc-sa/4.0/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/121917
Acceder
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oai_identifier_str oai:sedici.unlp.edu.ar:10915/121917
network_acronym_str SEDICI
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network_name_str SEDICI (UNLP)
spelling Fault tolerance in an amplifier system implemented in reconfigurable system on chip platformLovay, MónicaPeretti, GabrielaRomero, EduardoMarqués, CarlosIngenieríaHardware fault toleranceAmplifier systemSimulated annealing algorithmThis work address the problem of providing fault tolerance to an analog system embedded in a commercial programmable system on chip. The system presents a functionality that has to be maintained despite the presence of faults, without direct human intervention. For detecting a gain fault, we use a built-in self-test strategy that establishes the actual values of gain achievable by the system. A simulated annealing (SA) algorithm finds the hardware configuration. The simulation results show that the strategy is able to maintain its functionality under the presence of catastrophic and deviation faults. In addition, SA presents better performance than an exhaustive search method.Centro de Técnicas Analógico-Digitales2011-09info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdf131-136http://sedici.unlp.edu.ar/handle/10915/121917enginfo:eu-repo/semantics/altIdentifier/isbn/978-950-34-0749-3info:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-sa/4.0/Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-03T11:01:03Zoai:sedici.unlp.edu.ar:10915/121917Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-03 11:01:04.107SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv Fault tolerance in an amplifier system implemented in reconfigurable system on chip platform
title Fault tolerance in an amplifier system implemented in reconfigurable system on chip platform
spellingShingle Fault tolerance in an amplifier system implemented in reconfigurable system on chip platform
Lovay, Mónica
Ingeniería
Hardware fault tolerance
Amplifier system
Simulated annealing algorithm
title_short Fault tolerance in an amplifier system implemented in reconfigurable system on chip platform
title_full Fault tolerance in an amplifier system implemented in reconfigurable system on chip platform
title_fullStr Fault tolerance in an amplifier system implemented in reconfigurable system on chip platform
title_full_unstemmed Fault tolerance in an amplifier system implemented in reconfigurable system on chip platform
title_sort Fault tolerance in an amplifier system implemented in reconfigurable system on chip platform
dc.creator.none.fl_str_mv Lovay, Mónica
Peretti, Gabriela
Romero, Eduardo
Marqués, Carlos
author Lovay, Mónica
author_facet Lovay, Mónica
Peretti, Gabriela
Romero, Eduardo
Marqués, Carlos
author_role author
author2 Peretti, Gabriela
Romero, Eduardo
Marqués, Carlos
author2_role author
author
author
dc.subject.none.fl_str_mv Ingeniería
Hardware fault tolerance
Amplifier system
Simulated annealing algorithm
topic Ingeniería
Hardware fault tolerance
Amplifier system
Simulated annealing algorithm
dc.description.none.fl_txt_mv This work address the problem of providing fault tolerance to an analog system embedded in a commercial programmable system on chip. The system presents a functionality that has to be maintained despite the presence of faults, without direct human intervention. For detecting a gain fault, we use a built-in self-test strategy that establishes the actual values of gain achievable by the system. A simulated annealing (SA) algorithm finds the hardware configuration. The simulation results show that the strategy is able to maintain its functionality under the presence of catastrophic and deviation faults. In addition, SA presents better performance than an exhaustive search method.
Centro de Técnicas Analógico-Digitales
description This work address the problem of providing fault tolerance to an analog system embedded in a commercial programmable system on chip. The system presents a functionality that has to be maintained despite the presence of faults, without direct human intervention. For detecting a gain fault, we use a built-in self-test strategy that establishes the actual values of gain achievable by the system. A simulated annealing (SA) algorithm finds the hardware configuration. The simulation results show that the strategy is able to maintain its functionality under the presence of catastrophic and deviation faults. In addition, SA presents better performance than an exhaustive search method.
publishDate 2011
dc.date.none.fl_str_mv 2011-09
dc.type.none.fl_str_mv info:eu-repo/semantics/conferenceObject
info:eu-repo/semantics/publishedVersion
Objeto de conferencia
http://purl.org/coar/resource_type/c_5794
info:ar-repo/semantics/documentoDeConferencia
format conferenceObject
status_str publishedVersion
dc.identifier.none.fl_str_mv http://sedici.unlp.edu.ar/handle/10915/121917
url http://sedici.unlp.edu.ar/handle/10915/121917
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv info:eu-repo/semantics/altIdentifier/isbn/978-950-34-0749-3
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by-nc-sa/4.0/
Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc-sa/4.0/
Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)
dc.format.none.fl_str_mv application/pdf
131-136
dc.source.none.fl_str_mv reponame:SEDICI (UNLP)
instname:Universidad Nacional de La Plata
instacron:UNLP
reponame_str SEDICI (UNLP)
collection SEDICI (UNLP)
instname_str Universidad Nacional de La Plata
instacron_str UNLP
institution UNLP
repository.name.fl_str_mv SEDICI (UNLP) - Universidad Nacional de La Plata
repository.mail.fl_str_mv alira@sedici.unlp.edu.ar
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score 13.13397

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