A design method for active high-CMRR fully-differential circuits

Autores
Spinelli, Enrique Mario; Hornero, Gemma; Casas, Oscar; Haberman, Marcelo Alejandro
Año de publicación
2012
Idioma
inglés
Tipo de recurso
artículo
Estado
versión publicada
Descripción
A simple method for designing instrumentation fully-differential (FD) circuits based on standard single-ended (SE) operational amplifiers (OAs) is presented. It departs from a SE prototype that verifies the desired differential-mode transfer function, thereby leading to FD versions of the circuit. These circuits have a high common mode rejection ratio (CMRR), independent of component imbalances, and a unity common-mode gain. The proposed method does not allow the design of common-mode response, but it does verify common-mode stability, thus ensuring stable FD circuits. It is intended for instrumentation applications in which high CMRRs are required. The proposed approach makes it possible to design and implement inverter and non-inverter topologies as well. Design examples and experimental data are presented. Using general-purpose OAs and 5%-tolerance components, the CMRR of these circuits easily exceeds 90 to 100 dB.
Facultad de Ingeniería
Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales
Materia
Ingeniería
instrumentation circuits
operational amplifiers
OAs
differential circuits
fully-differential processing
analogue signal processing
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by-nc-sa/4.0/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/128256

id SEDICI_14661975b58bb77d3449336f6b6625d6
oai_identifier_str oai:sedici.unlp.edu.ar:10915/128256
network_acronym_str SEDICI
repository_id_str 1329
network_name_str SEDICI (UNLP)
spelling A design method for active high-CMRR fully-differential circuitsSpinelli, Enrique MarioHornero, GemmaCasas, OscarHaberman, Marcelo AlejandroIngenieríainstrumentation circuitsoperational amplifiersOAsdifferential circuitsfully-differential processinganalogue signal processingA simple method for designing instrumentation fully-differential (FD) circuits based on standard single-ended (SE) operational amplifiers (OAs) is presented. It departs from a SE prototype that verifies the desired differential-mode transfer function, thereby leading to FD versions of the circuit. These circuits have a high common mode rejection ratio (CMRR), independent of component imbalances, and a unity common-mode gain. The proposed method does not allow the design of common-mode response, but it does verify common-mode stability, thus ensuring stable FD circuits. It is intended for instrumentation applications in which high CMRRs are required. The proposed approach makes it possible to design and implement inverter and non-inverter topologies as well. Design examples and experimental data are presented. Using general-purpose OAs and 5%-tolerance components, the CMRR of these circuits easily exceeds 90 to 100 dB.Facultad de IngenieríaInstituto de Investigaciones en Electrónica, Control y Procesamiento de Señales2012info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionArticulohttp://purl.org/coar/resource_type/c_6501info:ar-repo/semantics/articuloapplication/pdf103-113http://sedici.unlp.edu.ar/handle/10915/128256enginfo:eu-repo/semantics/altIdentifier/issn/2043-7854info:eu-repo/semantics/altIdentifier/issn/2043-7862info:eu-repo/semantics/altIdentifier/doi/10.1504/ijit.2012.053281info:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-sa/4.0/Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-03T11:03:09Zoai:sedici.unlp.edu.ar:10915/128256Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-03 11:03:09.364SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv A design method for active high-CMRR fully-differential circuits
title A design method for active high-CMRR fully-differential circuits
spellingShingle A design method for active high-CMRR fully-differential circuits
Spinelli, Enrique Mario
Ingeniería
instrumentation circuits
operational amplifiers
OAs
differential circuits
fully-differential processing
analogue signal processing
title_short A design method for active high-CMRR fully-differential circuits
title_full A design method for active high-CMRR fully-differential circuits
title_fullStr A design method for active high-CMRR fully-differential circuits
title_full_unstemmed A design method for active high-CMRR fully-differential circuits
title_sort A design method for active high-CMRR fully-differential circuits
dc.creator.none.fl_str_mv Spinelli, Enrique Mario
Hornero, Gemma
Casas, Oscar
Haberman, Marcelo Alejandro
author Spinelli, Enrique Mario
author_facet Spinelli, Enrique Mario
Hornero, Gemma
Casas, Oscar
Haberman, Marcelo Alejandro
author_role author
author2 Hornero, Gemma
Casas, Oscar
Haberman, Marcelo Alejandro
author2_role author
author
author
dc.subject.none.fl_str_mv Ingeniería
instrumentation circuits
operational amplifiers
OAs
differential circuits
fully-differential processing
analogue signal processing
topic Ingeniería
instrumentation circuits
operational amplifiers
OAs
differential circuits
fully-differential processing
analogue signal processing
dc.description.none.fl_txt_mv A simple method for designing instrumentation fully-differential (FD) circuits based on standard single-ended (SE) operational amplifiers (OAs) is presented. It departs from a SE prototype that verifies the desired differential-mode transfer function, thereby leading to FD versions of the circuit. These circuits have a high common mode rejection ratio (CMRR), independent of component imbalances, and a unity common-mode gain. The proposed method does not allow the design of common-mode response, but it does verify common-mode stability, thus ensuring stable FD circuits. It is intended for instrumentation applications in which high CMRRs are required. The proposed approach makes it possible to design and implement inverter and non-inverter topologies as well. Design examples and experimental data are presented. Using general-purpose OAs and 5%-tolerance components, the CMRR of these circuits easily exceeds 90 to 100 dB.
Facultad de Ingeniería
Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales
description A simple method for designing instrumentation fully-differential (FD) circuits based on standard single-ended (SE) operational amplifiers (OAs) is presented. It departs from a SE prototype that verifies the desired differential-mode transfer function, thereby leading to FD versions of the circuit. These circuits have a high common mode rejection ratio (CMRR), independent of component imbalances, and a unity common-mode gain. The proposed method does not allow the design of common-mode response, but it does verify common-mode stability, thus ensuring stable FD circuits. It is intended for instrumentation applications in which high CMRRs are required. The proposed approach makes it possible to design and implement inverter and non-inverter topologies as well. Design examples and experimental data are presented. Using general-purpose OAs and 5%-tolerance components, the CMRR of these circuits easily exceeds 90 to 100 dB.
publishDate 2012
dc.date.none.fl_str_mv 2012
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
Articulo
http://purl.org/coar/resource_type/c_6501
info:ar-repo/semantics/articulo
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv http://sedici.unlp.edu.ar/handle/10915/128256
url http://sedici.unlp.edu.ar/handle/10915/128256
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv info:eu-repo/semantics/altIdentifier/issn/2043-7854
info:eu-repo/semantics/altIdentifier/issn/2043-7862
info:eu-repo/semantics/altIdentifier/doi/10.1504/ijit.2012.053281
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by-nc-sa/4.0/
Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc-sa/4.0/
Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)
dc.format.none.fl_str_mv application/pdf
103-113
dc.source.none.fl_str_mv reponame:SEDICI (UNLP)
instname:Universidad Nacional de La Plata
instacron:UNLP
reponame_str SEDICI (UNLP)
collection SEDICI (UNLP)
instname_str Universidad Nacional de La Plata
instacron_str UNLP
institution UNLP
repository.name.fl_str_mv SEDICI (UNLP) - Universidad Nacional de La Plata
repository.mail.fl_str_mv alira@sedici.unlp.edu.ar
_version_ 1842260529915101184
score 13.13397