Software Patterns for Asymmetric Multiprocessing Devices on Embedded Systems: a performance assessment

Autores
Martos, Pedro Ignacio Domingo; Garrido, Alejandra
Año de publicación
2017
Idioma
inglés
Tipo de recurso
documento de conferencia
Estado
versión publicada
Descripción
In emnedded systems there is a variant of Multicore System on Chip devices (MSoC devices) where not all the computing elements (processor cores) are equal. The differences in the cores of these devices range from different hardware architectures using the same instruction set to completely different processors working together inside the same device. These SoCs are called “Asymmetric Multi Processing Devices” (AMP Devices). In order to help developers to take advantage of the possinilities that these devices may offer in the context of emnedded systems, software design patterns have neen defined, descrining software architectural solutions with known uses. However, there are still no experimental results showing the nenefits of these solutions. In this work we measure the performance of a design pattern called Mini Me, applied on an AMP device configuration, and compare it against two Symmetric Multiprocessing Device (SMP Device) configurations. The evaluations show a netter than expected computing performance of the AMP Configuration using the design pattern Mini Me.
Laboratorio de Investigación y Formación en Informática Avanzada
Materia
Ingeniería Electrónica
Embedded Systems Patterns
Asymmetric Multiprocessing Patterns
Nivel de accesibilidad
acceso abierto
Condiciones de uso
http://creativecommons.org/licenses/by-nc-sa/4.0/
Repositorio
SEDICI (UNLP)
Institución
Universidad Nacional de La Plata
OAI Identificador
oai:sedici.unlp.edu.ar:10915/106031
Acceder
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oai_identifier_str oai:sedici.unlp.edu.ar:10915/106031
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repository_id_str 1329
network_name_str SEDICI (UNLP)
spelling Software Patterns for Asymmetric Multiprocessing Devices on Embedded Systems: a performance assessmentMartos, Pedro Ignacio DomingoGarrido, AlejandraIngeniería ElectrónicaEmbedded Systems PatternsAsymmetric Multiprocessing PatternsIn emnedded systems there is a variant of Multicore System on Chip devices (MSoC devices) where not all the computing elements (processor cores) are equal. The differences in the cores of these devices range from different hardware architectures using the same instruction set to completely different processors working together inside the same device. These SoCs are called “Asymmetric Multi Processing Devices” (AMP Devices). In order to help developers to take advantage of the possinilities that these devices may offer in the context of emnedded systems, software design patterns have neen defined, descrining software architectural solutions with known uses. However, there are still no experimental results showing the nenefits of these solutions. In this work we measure the performance of a design pattern called Mini Me, applied on an AMP device configuration, and compare it against two Symmetric Multiprocessing Device (SMP Device) configurations. The evaluations show a netter than expected computing performance of the AMP Configuration using the design pattern Mini Me.Laboratorio de Investigación y Formación en Informática Avanzada2017info:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionObjeto de conferenciahttp://purl.org/coar/resource_type/c_5794info:ar-repo/semantics/documentoDeConferenciaapplication/pdf41-46http://sedici.unlp.edu.ar/handle/10915/106031enginfo:eu-repo/semantics/altIdentifier/isbn/978-987-46297-1-5info:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-sa/4.0/Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)reponame:SEDICI (UNLP)instname:Universidad Nacional de La Platainstacron:UNLP2025-09-29T11:23:46Zoai:sedici.unlp.edu.ar:10915/106031Institucionalhttp://sedici.unlp.edu.ar/Universidad públicaNo correspondehttp://sedici.unlp.edu.ar/oai/snrdalira@sedici.unlp.edu.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:13292025-09-29 11:23:46.929SEDICI (UNLP) - Universidad Nacional de La Platafalse
dc.title.none.fl_str_mv Software Patterns for Asymmetric Multiprocessing Devices on Embedded Systems: a performance assessment
title Software Patterns for Asymmetric Multiprocessing Devices on Embedded Systems: a performance assessment
spellingShingle Software Patterns for Asymmetric Multiprocessing Devices on Embedded Systems: a performance assessment
Martos, Pedro Ignacio Domingo
Ingeniería Electrónica
Embedded Systems Patterns
Asymmetric Multiprocessing Patterns
title_short Software Patterns for Asymmetric Multiprocessing Devices on Embedded Systems: a performance assessment
title_full Software Patterns for Asymmetric Multiprocessing Devices on Embedded Systems: a performance assessment
title_fullStr Software Patterns for Asymmetric Multiprocessing Devices on Embedded Systems: a performance assessment
title_full_unstemmed Software Patterns for Asymmetric Multiprocessing Devices on Embedded Systems: a performance assessment
title_sort Software Patterns for Asymmetric Multiprocessing Devices on Embedded Systems: a performance assessment
dc.creator.none.fl_str_mv Martos, Pedro Ignacio Domingo
Garrido, Alejandra
author Martos, Pedro Ignacio Domingo
author_facet Martos, Pedro Ignacio Domingo
Garrido, Alejandra
author_role author
author2 Garrido, Alejandra
author2_role author
dc.subject.none.fl_str_mv Ingeniería Electrónica
Embedded Systems Patterns
Asymmetric Multiprocessing Patterns
topic Ingeniería Electrónica
Embedded Systems Patterns
Asymmetric Multiprocessing Patterns
dc.description.none.fl_txt_mv In emnedded systems there is a variant of Multicore System on Chip devices (MSoC devices) where not all the computing elements (processor cores) are equal. The differences in the cores of these devices range from different hardware architectures using the same instruction set to completely different processors working together inside the same device. These SoCs are called “Asymmetric Multi Processing Devices” (AMP Devices). In order to help developers to take advantage of the possinilities that these devices may offer in the context of emnedded systems, software design patterns have neen defined, descrining software architectural solutions with known uses. However, there are still no experimental results showing the nenefits of these solutions. In this work we measure the performance of a design pattern called Mini Me, applied on an AMP device configuration, and compare it against two Symmetric Multiprocessing Device (SMP Device) configurations. The evaluations show a netter than expected computing performance of the AMP Configuration using the design pattern Mini Me.
Laboratorio de Investigación y Formación en Informática Avanzada
description In emnedded systems there is a variant of Multicore System on Chip devices (MSoC devices) where not all the computing elements (processor cores) are equal. The differences in the cores of these devices range from different hardware architectures using the same instruction set to completely different processors working together inside the same device. These SoCs are called “Asymmetric Multi Processing Devices” (AMP Devices). In order to help developers to take advantage of the possinilities that these devices may offer in the context of emnedded systems, software design patterns have neen defined, descrining software architectural solutions with known uses. However, there are still no experimental results showing the nenefits of these solutions. In this work we measure the performance of a design pattern called Mini Me, applied on an AMP device configuration, and compare it against two Symmetric Multiprocessing Device (SMP Device) configurations. The evaluations show a netter than expected computing performance of the AMP Configuration using the design pattern Mini Me.
publishDate 2017
dc.date.none.fl_str_mv 2017
dc.type.none.fl_str_mv info:eu-repo/semantics/conferenceObject
info:eu-repo/semantics/publishedVersion
Objeto de conferencia
http://purl.org/coar/resource_type/c_5794
info:ar-repo/semantics/documentoDeConferencia
format conferenceObject
status_str publishedVersion
dc.identifier.none.fl_str_mv http://sedici.unlp.edu.ar/handle/10915/106031
url http://sedici.unlp.edu.ar/handle/10915/106031
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv info:eu-repo/semantics/altIdentifier/isbn/978-987-46297-1-5
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by-nc-sa/4.0/
Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc-sa/4.0/
Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)
dc.format.none.fl_str_mv application/pdf
41-46
dc.source.none.fl_str_mv reponame:SEDICI (UNLP)
instname:Universidad Nacional de La Plata
instacron:UNLP
reponame_str SEDICI (UNLP)
collection SEDICI (UNLP)
instname_str Universidad Nacional de La Plata
instacron_str UNLP
institution UNLP
repository.name.fl_str_mv SEDICI (UNLP) - Universidad Nacional de La Plata
repository.mail.fl_str_mv alira@sedici.unlp.edu.ar
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