Optimization of lookup schemes for flow-based packet classification on FPGAs

Autores
Zerbini, Carlos Albert; Finochietto, Jorge Manuel
Año de publicación
2015
Idioma
inglés
Tipo de recurso
artículo
Estado
versión publicada
Descripción
Packet classification has become a key processing function to enable future flow-based networking schemes. As network capacity increases and new services are deployed, both high throughput and reconfigurability are required for packet classification architectures. FPGA technology can provide the best trade-off among them. However, to date, lookup stages have been mostly developed as independent schemes from the classification stage, which makes their efficient integration on FPGAs difficult. In this context, we propose a new interpretation of the lookup problem in the general context of packet classification, which enables comparing existing lookup schemes on a common basis. From this analysis, we recognize new opportunities for optimization of lookup schemes and their associated classification schemes on FPGA. In particular, we focus on the most appropriate candidate for future networking needs and propose optimizations for it. To validate our analysis, we provide estimation and implementation results for typical lookup architectures on FPGA and observe their convenience for different lookup and classification cases, demonstrating the benefits of our proposed optimization.
Fil: Zerbini, Carlos Albert. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas, Físicas y Naturales; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Córdoba; Argentina. Universidad Tecnológica Nacional. Facultad Regional Córdoba; Argentina
Fil: Finochietto, Jorge Manuel. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Córdoba. Instituto de Estudios Avanzados en Ingeniería y Tecnología. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas Físicas y Naturales. Instituto de Estudios Avanzados en Ingeniería y Tecnología; Argentina
Materia
DATA NETWORKS
PACKET CLASSIFICATION
FPGA
LOOKUP SCHEMES
Nivel de accesibilidad
acceso abierto
Condiciones de uso
https://creativecommons.org/licenses/by/2.5/ar/
Repositorio
CONICET Digital (CONICET)
Institución
Consejo Nacional de Investigaciones Científicas y Técnicas
OAI Identificador
oai:ri.conicet.gov.ar:11336/102508

id CONICETDig_df927d4eef0170ed9d2b3bcae23a6190
oai_identifier_str oai:ri.conicet.gov.ar:11336/102508
network_acronym_str CONICETDig
repository_id_str 3498
network_name_str CONICET Digital (CONICET)
spelling Optimization of lookup schemes for flow-based packet classification on FPGAsZerbini, Carlos AlbertFinochietto, Jorge ManuelDATA NETWORKSPACKET CLASSIFICATIONFPGALOOKUP SCHEMEShttps://purl.org/becyt/ford/2.2https://purl.org/becyt/ford/2Packet classification has become a key processing function to enable future flow-based networking schemes. As network capacity increases and new services are deployed, both high throughput and reconfigurability are required for packet classification architectures. FPGA technology can provide the best trade-off among them. However, to date, lookup stages have been mostly developed as independent schemes from the classification stage, which makes their efficient integration on FPGAs difficult. In this context, we propose a new interpretation of the lookup problem in the general context of packet classification, which enables comparing existing lookup schemes on a common basis. From this analysis, we recognize new opportunities for optimization of lookup schemes and their associated classification schemes on FPGA. In particular, we focus on the most appropriate candidate for future networking needs and propose optimizations for it. To validate our analysis, we provide estimation and implementation results for typical lookup architectures on FPGA and observe their convenience for different lookup and classification cases, demonstrating the benefits of our proposed optimization.Fil: Zerbini, Carlos Albert. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas, Físicas y Naturales; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Córdoba; Argentina. Universidad Tecnológica Nacional. Facultad Regional Córdoba; ArgentinaFil: Finochietto, Jorge Manuel. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Córdoba. Instituto de Estudios Avanzados en Ingeniería y Tecnología. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas Físicas y Naturales. Instituto de Estudios Avanzados en Ingeniería y Tecnología; ArgentinaHindawi2015-03-08info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionhttp://purl.org/coar/resource_type/c_6501info:ar-repo/semantics/articuloapplication/pdfapplication/pdfapplication/pdfhttp://hdl.handle.net/11336/102508Zerbini, Carlos Albert; Finochietto, Jorge Manuel; Optimization of lookup schemes for flow-based packet classification on FPGAs; Hindawi; International Journal on Reconfigurable Computing; 2015; 8-3-2015; 1-311687-71951687-7209CONICET DigitalCONICETenginfo:eu-repo/semantics/altIdentifier/url/http://www.hindawi.com/journals/ijrc/2015/673596/cta/info:eu-repo/semantics/altIdentifier/doi/10.1155/2015/673596info:eu-repo/semantics/openAccesshttps://creativecommons.org/licenses/by/2.5/ar/reponame:CONICET Digital (CONICET)instname:Consejo Nacional de Investigaciones Científicas y Técnicas2025-09-10T13:14:05Zoai:ri.conicet.gov.ar:11336/102508instacron:CONICETInstitucionalhttp://ri.conicet.gov.ar/Organismo científico-tecnológicoNo correspondehttp://ri.conicet.gov.ar/oai/requestdasensio@conicet.gov.ar; lcarlino@conicet.gov.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:34982025-09-10 13:14:05.812CONICET Digital (CONICET) - Consejo Nacional de Investigaciones Científicas y Técnicasfalse
dc.title.none.fl_str_mv Optimization of lookup schemes for flow-based packet classification on FPGAs
title Optimization of lookup schemes for flow-based packet classification on FPGAs
spellingShingle Optimization of lookup schemes for flow-based packet classification on FPGAs
Zerbini, Carlos Albert
DATA NETWORKS
PACKET CLASSIFICATION
FPGA
LOOKUP SCHEMES
title_short Optimization of lookup schemes for flow-based packet classification on FPGAs
title_full Optimization of lookup schemes for flow-based packet classification on FPGAs
title_fullStr Optimization of lookup schemes for flow-based packet classification on FPGAs
title_full_unstemmed Optimization of lookup schemes for flow-based packet classification on FPGAs
title_sort Optimization of lookup schemes for flow-based packet classification on FPGAs
dc.creator.none.fl_str_mv Zerbini, Carlos Albert
Finochietto, Jorge Manuel
author Zerbini, Carlos Albert
author_facet Zerbini, Carlos Albert
Finochietto, Jorge Manuel
author_role author
author2 Finochietto, Jorge Manuel
author2_role author
dc.subject.none.fl_str_mv DATA NETWORKS
PACKET CLASSIFICATION
FPGA
LOOKUP SCHEMES
topic DATA NETWORKS
PACKET CLASSIFICATION
FPGA
LOOKUP SCHEMES
purl_subject.fl_str_mv https://purl.org/becyt/ford/2.2
https://purl.org/becyt/ford/2
dc.description.none.fl_txt_mv Packet classification has become a key processing function to enable future flow-based networking schemes. As network capacity increases and new services are deployed, both high throughput and reconfigurability are required for packet classification architectures. FPGA technology can provide the best trade-off among them. However, to date, lookup stages have been mostly developed as independent schemes from the classification stage, which makes their efficient integration on FPGAs difficult. In this context, we propose a new interpretation of the lookup problem in the general context of packet classification, which enables comparing existing lookup schemes on a common basis. From this analysis, we recognize new opportunities for optimization of lookup schemes and their associated classification schemes on FPGA. In particular, we focus on the most appropriate candidate for future networking needs and propose optimizations for it. To validate our analysis, we provide estimation and implementation results for typical lookup architectures on FPGA and observe their convenience for different lookup and classification cases, demonstrating the benefits of our proposed optimization.
Fil: Zerbini, Carlos Albert. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas, Físicas y Naturales; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Córdoba; Argentina. Universidad Tecnológica Nacional. Facultad Regional Córdoba; Argentina
Fil: Finochietto, Jorge Manuel. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Córdoba. Instituto de Estudios Avanzados en Ingeniería y Tecnología. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas Físicas y Naturales. Instituto de Estudios Avanzados en Ingeniería y Tecnología; Argentina
description Packet classification has become a key processing function to enable future flow-based networking schemes. As network capacity increases and new services are deployed, both high throughput and reconfigurability are required for packet classification architectures. FPGA technology can provide the best trade-off among them. However, to date, lookup stages have been mostly developed as independent schemes from the classification stage, which makes their efficient integration on FPGAs difficult. In this context, we propose a new interpretation of the lookup problem in the general context of packet classification, which enables comparing existing lookup schemes on a common basis. From this analysis, we recognize new opportunities for optimization of lookup schemes and their associated classification schemes on FPGA. In particular, we focus on the most appropriate candidate for future networking needs and propose optimizations for it. To validate our analysis, we provide estimation and implementation results for typical lookup architectures on FPGA and observe their convenience for different lookup and classification cases, demonstrating the benefits of our proposed optimization.
publishDate 2015
dc.date.none.fl_str_mv 2015-03-08
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
http://purl.org/coar/resource_type/c_6501
info:ar-repo/semantics/articulo
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv http://hdl.handle.net/11336/102508
Zerbini, Carlos Albert; Finochietto, Jorge Manuel; Optimization of lookup schemes for flow-based packet classification on FPGAs; Hindawi; International Journal on Reconfigurable Computing; 2015; 8-3-2015; 1-31
1687-7195
1687-7209
CONICET Digital
CONICET
url http://hdl.handle.net/11336/102508
identifier_str_mv Zerbini, Carlos Albert; Finochietto, Jorge Manuel; Optimization of lookup schemes for flow-based packet classification on FPGAs; Hindawi; International Journal on Reconfigurable Computing; 2015; 8-3-2015; 1-31
1687-7195
1687-7209
CONICET Digital
CONICET
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv info:eu-repo/semantics/altIdentifier/url/http://www.hindawi.com/journals/ijrc/2015/673596/cta/
info:eu-repo/semantics/altIdentifier/doi/10.1155/2015/673596
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
https://creativecommons.org/licenses/by/2.5/ar/
eu_rights_str_mv openAccess
rights_invalid_str_mv https://creativecommons.org/licenses/by/2.5/ar/
dc.format.none.fl_str_mv application/pdf
application/pdf
application/pdf
dc.publisher.none.fl_str_mv Hindawi
publisher.none.fl_str_mv Hindawi
dc.source.none.fl_str_mv reponame:CONICET Digital (CONICET)
instname:Consejo Nacional de Investigaciones Científicas y Técnicas
reponame_str CONICET Digital (CONICET)
collection CONICET Digital (CONICET)
instname_str Consejo Nacional de Investigaciones Científicas y Técnicas
repository.name.fl_str_mv CONICET Digital (CONICET) - Consejo Nacional de Investigaciones Científicas y Técnicas
repository.mail.fl_str_mv dasensio@conicet.gov.ar; lcarlino@conicet.gov.ar
_version_ 1842980750531493888
score 12.993085