Heterogeneous Capacitor‐less Two‐transistor Dynamic Random Access Memory Cell with Long Retention Time and High Sensing Current Supporting 5‐Bit Multilevel Operation

Autores
Lee, Yonghee; Lee, Seung Yoon; Choi, Jinheon; Ghenzi, Néstor; Han, Joon Kyu; Hwang, Cheol Seong
Año de publicación
2025
Idioma
inglés
Tipo de recurso
artículo
Estado
versión publicada
Descripción
A heterogeneous capacitor-less two-transistor (2T0C) dynamic random accessmemory (DRAM) cell is fabricated, featuring a write transistor with an amorphousindium–gallium–zinc–oxide (a-IGZO) channel and a read transistor with asingle crystal silicon (Si) channel. These transistors are vertically integrated toachieve high integration density. A data retention time of over 4800 s is achieveddue to the wide bandgap of a-IGZO, and a high sensing current of over166 μA μm1 is achieved due to the high mobility of the Si. This high sensingcurrent allows for a short read latency of 1.34 ns and 5-bit multilevel celloperation, the highest reported for 2T0C DRAM cells.
Fil: Lee, Yonghee. Seoul National University; Corea del Sur
Fil: Lee, Seung Yoon. Seoul National University; Corea del Sur
Fil: Choi, Jinheon. Seoul National University; Corea del Sur
Fil: Ghenzi, Néstor. Universidad Nacional de Avellaneda. Departamento de Prod. y Trabajo; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina
Fil: Han, Joon Kyu. Seoul National University; Corea del Sur
Fil: Hwang, Cheol Seong. Seoul National University; Corea del Sur
Materia
transistor
analog
2t0c
memory
Nivel de accesibilidad
acceso abierto
Condiciones de uso
https://creativecommons.org/licenses/by-nc-nd/2.5/ar/
Repositorio
CONICET Digital (CONICET)
Institución
Consejo Nacional de Investigaciones Científicas y Técnicas
OAI Identificador
oai:ri.conicet.gov.ar:11336/271609
Acceder
id CONICETDig_61a69e960783a849bedd722aee830121
oai_identifier_str oai:ri.conicet.gov.ar:11336/271609
network_acronym_str CONICETDig
repository_id_str 3498
network_name_str CONICET Digital (CONICET)
spelling Heterogeneous Capacitor‐less Two‐transistor Dynamic Random Access Memory Cell with Long Retention Time and High Sensing Current Supporting 5‐Bit Multilevel OperationLee, YongheeLee, Seung YoonChoi, JinheonGhenzi, NéstorHan, Joon KyuHwang, Cheol Seongtransistoranalog2t0cmemoryhttps://purl.org/becyt/ford/1.3https://purl.org/becyt/ford/1A heterogeneous capacitor-less two-transistor (2T0C) dynamic random accessmemory (DRAM) cell is fabricated, featuring a write transistor with an amorphousindium–gallium–zinc–oxide (a-IGZO) channel and a read transistor with asingle crystal silicon (Si) channel. These transistors are vertically integrated toachieve high integration density. A data retention time of over 4800 s is achieveddue to the wide bandgap of a-IGZO, and a high sensing current of over166 μA μm1 is achieved due to the high mobility of the Si. This high sensingcurrent allows for a short read latency of 1.34 ns and 5-bit multilevel celloperation, the highest reported for 2T0C DRAM cells.Fil: Lee, Yonghee. Seoul National University; Corea del SurFil: Lee, Seung Yoon. Seoul National University; Corea del SurFil: Choi, Jinheon. Seoul National University; Corea del SurFil: Ghenzi, Néstor. Universidad Nacional de Avellaneda. Departamento de Prod. y Trabajo; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Han, Joon Kyu. Seoul National University; Corea del SurFil: Hwang, Cheol Seong. Seoul National University; Corea del SurWiley VCH Verlag2025-05info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionhttp://purl.org/coar/resource_type/c_6501info:ar-repo/semantics/articuloapplication/pdfapplication/pdfhttp://hdl.handle.net/11336/271609Lee, Yonghee; Lee, Seung Yoon; Choi, Jinheon; Ghenzi, Néstor; Han, Joon Kyu; et al.; Heterogeneous Capacitor‐less Two‐transistor Dynamic Random Access Memory Cell with Long Retention Time and High Sensing Current Supporting 5‐Bit Multilevel Operation; Wiley VCH Verlag; Physica Status Solidi-rapid Research Letters; 5-2025; 1-61862-6254CONICET DigitalCONICETenginfo:eu-repo/semantics/altIdentifier/url/https://onlinelibrary.wiley.com/doi/10.1002/pssr.202500131info:eu-repo/semantics/altIdentifier/doi/10.1002/pssr.202500131info:eu-repo/semantics/openAccesshttps://creativecommons.org/licenses/by-nc-nd/2.5/ar/reponame:CONICET Digital (CONICET)instname:Consejo Nacional de Investigaciones Científicas y Técnicas2025-09-29T10:06:37Zoai:ri.conicet.gov.ar:11336/271609instacron:CONICETInstitucionalhttp://ri.conicet.gov.ar/Organismo científico-tecnológicoNo correspondehttp://ri.conicet.gov.ar/oai/requestdasensio@conicet.gov.ar; lcarlino@conicet.gov.arArgentinaNo correspondeNo correspondeNo correspondeopendoar:34982025-09-29 10:06:37.94CONICET Digital (CONICET) - Consejo Nacional de Investigaciones Científicas y Técnicasfalse
dc.title.none.fl_str_mv Heterogeneous Capacitor‐less Two‐transistor Dynamic Random Access Memory Cell with Long Retention Time and High Sensing Current Supporting 5‐Bit Multilevel Operation
title Heterogeneous Capacitor‐less Two‐transistor Dynamic Random Access Memory Cell with Long Retention Time and High Sensing Current Supporting 5‐Bit Multilevel Operation
spellingShingle Heterogeneous Capacitor‐less Two‐transistor Dynamic Random Access Memory Cell with Long Retention Time and High Sensing Current Supporting 5‐Bit Multilevel Operation
Lee, Yonghee
transistor
analog
2t0c
memory
title_short Heterogeneous Capacitor‐less Two‐transistor Dynamic Random Access Memory Cell with Long Retention Time and High Sensing Current Supporting 5‐Bit Multilevel Operation
title_full Heterogeneous Capacitor‐less Two‐transistor Dynamic Random Access Memory Cell with Long Retention Time and High Sensing Current Supporting 5‐Bit Multilevel Operation
title_fullStr Heterogeneous Capacitor‐less Two‐transistor Dynamic Random Access Memory Cell with Long Retention Time and High Sensing Current Supporting 5‐Bit Multilevel Operation
title_full_unstemmed Heterogeneous Capacitor‐less Two‐transistor Dynamic Random Access Memory Cell with Long Retention Time and High Sensing Current Supporting 5‐Bit Multilevel Operation
title_sort Heterogeneous Capacitor‐less Two‐transistor Dynamic Random Access Memory Cell with Long Retention Time and High Sensing Current Supporting 5‐Bit Multilevel Operation
dc.creator.none.fl_str_mv Lee, Yonghee
Lee, Seung Yoon
Choi, Jinheon
Ghenzi, Néstor
Han, Joon Kyu
Hwang, Cheol Seong
author Lee, Yonghee
author_facet Lee, Yonghee
Lee, Seung Yoon
Choi, Jinheon
Ghenzi, Néstor
Han, Joon Kyu
Hwang, Cheol Seong
author_role author
author2 Lee, Seung Yoon
Choi, Jinheon
Ghenzi, Néstor
Han, Joon Kyu
Hwang, Cheol Seong
author2_role author
author
author
author
author
dc.subject.none.fl_str_mv transistor
analog
2t0c
memory
topic transistor
analog
2t0c
memory
purl_subject.fl_str_mv https://purl.org/becyt/ford/1.3
https://purl.org/becyt/ford/1
dc.description.none.fl_txt_mv A heterogeneous capacitor-less two-transistor (2T0C) dynamic random accessmemory (DRAM) cell is fabricated, featuring a write transistor with an amorphousindium–gallium–zinc–oxide (a-IGZO) channel and a read transistor with asingle crystal silicon (Si) channel. These transistors are vertically integrated toachieve high integration density. A data retention time of over 4800 s is achieveddue to the wide bandgap of a-IGZO, and a high sensing current of over166 μA μm1 is achieved due to the high mobility of the Si. This high sensingcurrent allows for a short read latency of 1.34 ns and 5-bit multilevel celloperation, the highest reported for 2T0C DRAM cells.
Fil: Lee, Yonghee. Seoul National University; Corea del Sur
Fil: Lee, Seung Yoon. Seoul National University; Corea del Sur
Fil: Choi, Jinheon. Seoul National University; Corea del Sur
Fil: Ghenzi, Néstor. Universidad Nacional de Avellaneda. Departamento de Prod. y Trabajo; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina
Fil: Han, Joon Kyu. Seoul National University; Corea del Sur
Fil: Hwang, Cheol Seong. Seoul National University; Corea del Sur
description A heterogeneous capacitor-less two-transistor (2T0C) dynamic random accessmemory (DRAM) cell is fabricated, featuring a write transistor with an amorphousindium–gallium–zinc–oxide (a-IGZO) channel and a read transistor with asingle crystal silicon (Si) channel. These transistors are vertically integrated toachieve high integration density. A data retention time of over 4800 s is achieveddue to the wide bandgap of a-IGZO, and a high sensing current of over166 μA μm1 is achieved due to the high mobility of the Si. This high sensingcurrent allows for a short read latency of 1.34 ns and 5-bit multilevel celloperation, the highest reported for 2T0C DRAM cells.
publishDate 2025
dc.date.none.fl_str_mv 2025-05
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
http://purl.org/coar/resource_type/c_6501
info:ar-repo/semantics/articulo
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv http://hdl.handle.net/11336/271609
Lee, Yonghee; Lee, Seung Yoon; Choi, Jinheon; Ghenzi, Néstor; Han, Joon Kyu; et al.; Heterogeneous Capacitor‐less Two‐transistor Dynamic Random Access Memory Cell with Long Retention Time and High Sensing Current Supporting 5‐Bit Multilevel Operation; Wiley VCH Verlag; Physica Status Solidi-rapid Research Letters; 5-2025; 1-6
1862-6254
CONICET Digital
CONICET
url http://hdl.handle.net/11336/271609
identifier_str_mv Lee, Yonghee; Lee, Seung Yoon; Choi, Jinheon; Ghenzi, Néstor; Han, Joon Kyu; et al.; Heterogeneous Capacitor‐less Two‐transistor Dynamic Random Access Memory Cell with Long Retention Time and High Sensing Current Supporting 5‐Bit Multilevel Operation; Wiley VCH Verlag; Physica Status Solidi-rapid Research Letters; 5-2025; 1-6
1862-6254
CONICET Digital
CONICET
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv info:eu-repo/semantics/altIdentifier/url/https://onlinelibrary.wiley.com/doi/10.1002/pssr.202500131
info:eu-repo/semantics/altIdentifier/doi/10.1002/pssr.202500131
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
https://creativecommons.org/licenses/by-nc-nd/2.5/ar/
eu_rights_str_mv openAccess
rights_invalid_str_mv https://creativecommons.org/licenses/by-nc-nd/2.5/ar/
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv Wiley VCH Verlag
publisher.none.fl_str_mv Wiley VCH Verlag
dc.source.none.fl_str_mv reponame:CONICET Digital (CONICET)
instname:Consejo Nacional de Investigaciones Científicas y Técnicas
reponame_str CONICET Digital (CONICET)
collection CONICET Digital (CONICET)
instname_str Consejo Nacional de Investigaciones Científicas y Técnicas
repository.name.fl_str_mv CONICET Digital (CONICET) - Consejo Nacional de Investigaciones Científicas y Técnicas
repository.mail.fl_str_mv dasensio@conicet.gov.ar; lcarlino@conicet.gov.ar
_version_ 1844613917442048000
score 13.070432

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