FPGA-Based Digital filters using Bit-Serial arithmetic

Authors
Arroyuelo, Mónica; Arroyuelo, Jorge; Grosso, Alejandro
Publication Year
2007
Language
Spanish
Format
conference paper
Status
Published version
Description
This paper presents an efficient method for implementation of digital filters targeted FPGA architectures. The traditional approach is based on application of general purpose multipliers. However, multipliers implemented in FPGA architectures do not allow to construct economic Digital Filters. For this reason, multipliers are replaced by Lookup Tables and Adder-Substractor, which use Bit-Serial Arithmetic. Lookup Tables can be of considerable size in high order filters, thus interconnection techniques will be used to construct high order filters from a set of low order filters. The paper presents several examples confirming that these techniques allow a reduction in logic cells utilization of filters implementation based on Bit-Serial Arithmetic concept.
II Workshop de Arquitecturas, Redes y Sistemas Operativos
Red de Universidades con Carreras en Informática (RedUNCI)
Subject
Ciencias Informáticas
Informática
Access level
Open access
License
Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
Repository
SEDICI (UNLP)
Institution
Universidad Nacional de La Plata
OAI Identifier
oai:sedici.unlp.edu.ar:10915/21693