Metrics for FIR Filters based on distributed arithmetic in FPGA

Authors
Vázquez, Martín; Simonelli, Daniel Horacio; Acosta, Nelson
Publication Year
2004
Language
English
Format
conference paper
Status
Published version
Description
In this paper, metrics regarding different architectures for distributed arithmetic based FIR filters in FPGA are presented. Main filter parameters are described as well as diverse design techniques applied: pipelining, bit-serial, digit-serial y bit-parallel. Each filter description was written in VHDL at RTL level. For achieving this goal no relative location (rloc) technique was used what redounds on more generic and expensive designs than those available through Core Generator tool. Implementation has been carried out over FPGAs belonging to Xilinx Virtex II family.
Eje: IV - Workshop de procesamiento distribuido y paralelo
Red de Universidades con Carreras en Informática (RedUNCI)
Subject
Ciencias Informáticas
Parallel processing
Distributed
Metrics
distributed arithmetic
FPGA
FIR
Access level
Open access
License
Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Argentina (CC BY-NC-SA 2.5)
Repository
SEDICI (UNLP)
Institution
Universidad Nacional de La Plata
OAI Identifier
oai:sedici.unlp.edu.ar:10915/22495